Hochschulschrift
Preserving high resolution in deep-submicron CMOS pipelined A D converters
- Location
-
Deutsche Nationalbibliothek Frankfurt am Main
- ISBN
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9783866283169
- Dimensions
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21 cm
- Extent
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XXIII, 237 S.
- Edition
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1. ed.
- Language
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Englisch
- Notes
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Ill., graph. Darst.
Zugl.: Zürich, Techn. Hochsch., Diss., 2010
- Bibliographic citation
-
Series in microelectronics ; Vol. 206
- Classification
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Elektrotechnik, Elektronik
- Keyword
-
Analog-Digital-Umsetzer
Betriebsspannung
Analogschaltung
CMOS
- Event
-
Veröffentlichung
- (where)
-
Konstanz
- (who)
-
Hartung-Gorre
- (when)
-
2010
- Creator
- Table of contents
- Rights
-
Bei diesem Objekt liegt nur das Inhaltsverzeichnis digital vor. Der Zugriff darauf ist unbeschränkt möglich.
- Last update
-
11.06.2025, 1:41 PM CEST
Data provider
This object is provided by:
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Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Object type
- Hochschulschrift
Associated
- Treichler, Jürg Andreas
- Hartung-Gorre
Time of origin
- 2010
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Realistic gate model for efficient timing analysis of very deep submicron CMOS circuits
Quantitative Optimization of Highly Efficient Dedicated CORDIC Macros for SoCs in Deep-Submicron CMOS Technologies
CMOS A-D-converters using MOSFET-only R-2R ladders
Voraussetzungen für die Fertigung von 50 V MOS-Transistoren in einem Sub-Micron CMOS-Prozess
High-level optimization of performance and power in very deep sub-micron interconnects
Accurate power estimation of deep-submicron VLSI circuits considering delay effects and glitches
High-level optimization of performance and power in very deep sub-micron interconnects
Prinzipien der Verkleinerung von Submicron CMOS-Schaltungen: eine Untersuchung zu den durch Verbindungsleitungen hervorgerufenen Begrenzungen höchstintegrierter Schaltungen
Deep-submicron full-custom VLSI-design of highly optimized high-throughput low-latency LDPC decoders
Low voltage hot carrier issues in deep sub-micron metal oxide semiconductor field effect transistors
Development of pixel front-end electronics using advanced deep submicron CMOS technologies
Development of pixel front-end electronics using advanced deep submicron CMOS technologies
Realistic gate model for efficient timing analysis of very deep submicron CMOS circuits
Quantitative Optimization of Highly Efficient Dedicated CORDIC Macros for SoCs in Deep-Submicron CMOS Technologies
CMOS A-D-converters using MOSFET-only R-2R ladders
Voraussetzungen für die Fertigung von 50 V MOS-Transistoren in einem Sub-Micron CMOS-Prozess
High-level optimization of performance and power in very deep sub-micron interconnects
Accurate power estimation of deep-submicron VLSI circuits considering delay effects and glitches
High-level optimization of performance and power in very deep sub-micron interconnects
Prinzipien der Verkleinerung von Submicron CMOS-Schaltungen: eine Untersuchung zu den durch Verbindungsleitungen hervorgerufenen Begrenzungen höchstintegrierter Schaltungen
Deep-submicron full-custom VLSI-design of highly optimized high-throughput low-latency LDPC decoders