Accurate power estimation of deep-submicron VLSI circuits considering delay effects and glitches
- Weitere Titel
-
Genaue Verlustleistungsvorhersage hochintegrierter Digitalschaltungen unter Berücksichtigung von Laufzeiteffekten und Glitches
- Standort
-
Deutsche Nationalbibliothek Frankfurt am Main
- Umfang
-
Online-Ressource
- Sprache
-
Englisch
- Anmerkungen
-
Rheinisch-Westfälische Technische Hochschule Aachen, Dissertation, 2019
- Klassifikation
-
Elektrotechnik, Elektronik
- Schlagwort
-
Integrated circuits--Very large scale integration
- Ereignis
-
Veröffentlichung
- (wo)
-
Aachen
- (wer)
-
Universitätsbibliothek der RWTH Aachen
- (wann)
-
2019
- Urheber
- Beteiligte Personen und Organisationen
- DOI
-
10.18154/RWTH-2019-06005
- URN
-
urn:nbn:de:101:1-2019091906100455319434
- Rechteinformation
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Letzte Aktualisierung
-
25.03.2025, 13:47 MEZ
Datenpartner
Dieses Objekt wird bereitgestellt von:
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Beteiligte
- Meixner, Michael
- Noll, Tobias G.
- Negra, Renato
- Gemmeke, Tobias
- Universitätsbibliothek der RWTH Aachen
Entstanden
- 2019
Ähnliche Objekte (12)
VLSI circuits for MIMO preprocessing
VLSI circuits for cryptographic authentication
Efficient quadratic placement of VLSI circuits
Efficient algorithms for fundamental statistical timing analysis problems in delay test applications of VLSI circuits
VLSI circuits for MIMO-OFDM physical layer
Design of VLSI circuits : based on VENUS
Routing congestion in VLSI circuits : estimation and optimization
The design of high-speed dynamic CMOS circuits for VLSI
Deep-submicron full-custom VLSI-design of highly optimized high-throughput low-latency LDPC decoders
Deep-submicron full-custom VLSI-design of highly optimized high-throughput low-latency LDPC decoders
Realistic gate model for efficient timing analysis of very deep submicron CMOS circuits
Model reduction of parasitic coupling networks of mixed-signal VLSI circuits
VLSI circuits for MIMO preprocessing
VLSI circuits for cryptographic authentication
Efficient quadratic placement of VLSI circuits
Efficient algorithms for fundamental statistical timing analysis problems in delay test applications of VLSI circuits
VLSI circuits for MIMO-OFDM physical layer
Design of VLSI circuits : based on VENUS
Routing congestion in VLSI circuits : estimation and optimization
The design of high-speed dynamic CMOS circuits for VLSI
Deep-submicron full-custom VLSI-design of highly optimized high-throughput low-latency LDPC decoders
Deep-submicron full-custom VLSI-design of highly optimized high-throughput low-latency LDPC decoders
Realistic gate model for efficient timing analysis of very deep submicron CMOS circuits
Model reduction of parasitic coupling networks of mixed-signal VLSI circuits
VLSI circuits for MIMO preprocessing
VLSI circuits for cryptographic authentication
Efficient quadratic placement of VLSI circuits
Efficient algorithms for fundamental statistical timing analysis problems in delay test applications of VLSI circuits
VLSI circuits for MIMO-OFDM physical layer
Design of VLSI circuits : based on VENUS
Routing congestion in VLSI circuits : estimation and optimization
The design of high-speed dynamic CMOS circuits for VLSI
Deep-submicron full-custom VLSI-design of highly optimized high-throughput low-latency LDPC decoders
Deep-submicron full-custom VLSI-design of highly optimized high-throughput low-latency LDPC decoders
Realistic gate model for efficient timing analysis of very deep submicron CMOS circuits