Hochschulschrift
Retargetable processor system integration into multi-processor system on chip platforms
- Standort
-
Deutsche Nationalbibliothek Frankfurt am Main
- ISBN
-
9781402085741
- Maße
-
24 cm
- Umfang
-
XIV, 162 S.
- Sprache
-
Englisch
- Anmerkungen
-
graph. Darst.
Zugl.: Aachen, Techn. Hochsch., Diss., A. Wieferink, 2007
- Klassifikation
-
Elektrotechnik, Elektronik
- Schlagwort
-
System-on-Chip
Mehrprozessorsystem
Entwurfsautomation
System-on-Chip
Mehrprozessorsystem
Systemplattform
- Ereignis
-
Veröffentlichung
- (wo)
-
[Dordrecht]
- (wer)
-
Springer
- (wann)
-
2008
- Urheber
- Inhaltsverzeichnis
- Rechteinformation
-
Bei diesem Objekt liegt nur das Inhaltsverzeichnis digital vor. Der Zugriff darauf ist unbeschränkt möglich.
- Letzte Aktualisierung
-
11.06.2025, 14:20 MESZ
Datenpartner
Dieses Objekt wird bereitgestellt von:
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Objekttyp
- Hochschulschrift
Beteiligte
- Wieferink, Andreas
- Meyr, Heinrich
- Leupers, Rainer
- Springer
Entstanden
- 2008
Ähnliche Objekte (12)
Integrated system level modeling of network on chip enabled multi-processor platforms
High-level estimation and exploration of reliability for multi-processor system-on-chip
Efficient and predictable thread synchronization mechanisms for mixed-criticality systems on shared-memory multi-processor platforms
A flexible multi-processor system-on-a-chip architecture for safety- and security-critical applications
Model-based exploration of parallelism in context of automotive multi-processor systems
Program reversal schedules for single and multi-processor machines
Program reversal schedules for single and multi-processor machines
Demonstration of run-time spatial mapping of streaming applications to a heterogeneous multi-processor system-on-chip (MPSOC)
Design concepts for a virtualizable embedded MPSoC architecture : enabling virtualization in embedded multi-processor systems
Materialisation and parallelism in the mapping of an object model to a relational multi-processor system
KEP2 (Kiel Esterel Processor 2) THE ESTEREL PROCESSOR
Predicting cache contention in multicore processor systems
Integrated system level modeling of network on chip enabled multi-processor platforms
High-level estimation and exploration of reliability for multi-processor system-on-chip
Efficient and predictable thread synchronization mechanisms for mixed-criticality systems on shared-memory multi-processor platforms
A flexible multi-processor system-on-a-chip architecture for safety- and security-critical applications
Model-based exploration of parallelism in context of automotive multi-processor systems
Program reversal schedules for single and multi-processor machines
Program reversal schedules for single and multi-processor machines
Demonstration of run-time spatial mapping of streaming applications to a heterogeneous multi-processor system-on-chip (MPSOC)
Design concepts for a virtualizable embedded MPSoC architecture : enabling virtualization in embedded multi-processor systems
Materialisation and parallelism in the mapping of an object model to a relational multi-processor system
KEP2 (Kiel Esterel Processor 2) THE ESTEREL PROCESSOR
Predicting cache contention in multicore processor systems
Integrated system level modeling of network on chip enabled multi-processor platforms
High-level estimation and exploration of reliability for multi-processor system-on-chip
Efficient and predictable thread synchronization mechanisms for mixed-criticality systems on shared-memory multi-processor platforms
A flexible multi-processor system-on-a-chip architecture for safety- and security-critical applications
Model-based exploration of parallelism in context of automotive multi-processor systems
Program reversal schedules for single and multi-processor machines
Program reversal schedules for single and multi-processor machines
Demonstration of run-time spatial mapping of streaming applications to a heterogeneous multi-processor system-on-chip (MPSOC)
Design concepts for a virtualizable embedded MPSoC architecture : enabling virtualization in embedded multi-processor systems
Materialisation and parallelism in the mapping of an object model to a relational multi-processor system
KEP2 (Kiel Esterel Processor 2) THE ESTEREL PROCESSOR