Hochschulschrift
A flexible multi-processor system-on-a-chip architecture for safety- and security-critical applications
- Location
-
Deutsche Nationalbibliothek Frankfurt am Main
- ISBN
-
9783844022681
- Dimensions
-
30 cm, 311 g
- Extent
-
IX, 192 S.
- Language
-
Englisch
- Notes
-
Ill., graph. Darst.
Zugl.: Hamburg, Techn. Univ., Diss., 2013
- Classification
-
Elektrotechnik, Elektronik
- Keyword
-
Sicherheitskritisches System
Eingebettetes System
Mehrprozessorsystem
System-on-Chip
Field programmable gate array
Bridge
Cache-Speicher
Speicherorganisation
Benchmark
Testen
- Table of contents
- Rights
-
Bei diesem Objekt liegt nur das Inhaltsverzeichnis digital vor. Der Zugriff darauf ist unbeschränkt möglich.
- Last update
-
11.03.2025, 11:51 AM CET
Data provider
This object is provided by:
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Object type
- Hochschulschrift
Associated
- Kliem, Daniel
- Shaker
Time of origin
- 2013
Other Objects (12)
Retargetable processor system integration into multi-processor system on chip platforms
A survey on formal verification techniques for safety-critical systems-on-chip
Safety Recommendations for Safety-Critical Design Patterns
Efficient and flexible cryptographic co-processor architecture for server application
Safety critical wireless sensor networks
Integrated system level modeling of network on chip enabled multi-processor platforms
KEP2 (Kiel Esterel Processor 2) THE ESTEREL PROCESSOR
High-level estimation and exploration of reliability for multi-processor system-on-chip
Run-time redundancy management of processor functional units for mixed-critical scenarios
Safety-Critical Control for Ensemble Systems
The Kiel Esterel processor : a multi-threaded reactive processor
Industrial perspectives of safety critical systems : proceedings of the Sixth Safety Critical Systems Symposium, Birmingham 1998
Retargetable processor system integration into multi-processor system on chip platforms
A survey on formal verification techniques for safety-critical systems-on-chip
Safety Recommendations for Safety-Critical Design Patterns
Efficient and flexible cryptographic co-processor architecture for server application
Safety critical wireless sensor networks
Integrated system level modeling of network on chip enabled multi-processor platforms
KEP2 (Kiel Esterel Processor 2) THE ESTEREL PROCESSOR
High-level estimation and exploration of reliability for multi-processor system-on-chip
Run-time redundancy management of processor functional units for mixed-critical scenarios
Safety-Critical Control for Ensemble Systems
The Kiel Esterel processor : a multi-threaded reactive processor
Industrial perspectives of safety critical systems : proceedings of the Sixth Safety Critical Systems Symposium, Birmingham 1998
Retargetable processor system integration into multi-processor system on chip platforms
A survey on formal verification techniques for safety-critical systems-on-chip
Safety Recommendations for Safety-Critical Design Patterns
Efficient and flexible cryptographic co-processor architecture for server application
Safety critical wireless sensor networks
Integrated system level modeling of network on chip enabled multi-processor platforms
KEP2 (Kiel Esterel Processor 2) THE ESTEREL PROCESSOR
High-level estimation and exploration of reliability for multi-processor system-on-chip
Run-time redundancy management of processor functional units for mixed-critical scenarios
Safety-Critical Control for Ensemble Systems
The Kiel Esterel processor : a multi-threaded reactive processor