Model reduction of parasitic coupling networks of mixed-signal VLSI circuits
- Standort
-
Deutsche Nationalbibliothek Frankfurt am Main
- Umfang
-
Online-Ressource
- Sprache
-
Englisch
- Erschienen in
-
In: Ludwig, S.; Mathis, W.: Model reduction of parasitic coupling networks of mixed-signal VLSI circuits. In: COMPEL - The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 30 (2011), Nr. 4, S. 1363-1375. DOI: https://doi.org/10.1108/03321641111133253
- Klassifikation
-
Elektrotechnik, Elektronik
- Ereignis
-
Veröffentlichung
- (wo)
-
Hannover
- (wer)
-
Gottfried Wilhelm Leibniz Universität Hannover
- (wann)
-
2011
- Ereignis
-
Veröffentlichung
- (wo)
-
Hannover
- (wer)
-
Technische Informationsbibliothek (TIB)
- (wann)
-
2011
- DOI
-
10.15488/2740
- URN
-
urn:nbn:de:101:1-2020062307053589038986
- Rechteinformation
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Letzte Aktualisierung
-
14.08.2025, 10:58 MESZ
Datenpartner
Dieses Objekt wird bereitgestellt von:
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Beteiligte
- Gottfried Wilhelm Leibniz Universität Hannover
- Technische Informationsbibliothek (TIB)
Entstanden
- 2011
Ähnliche Objekte (12)
VLSI circuits for MIMO preprocessing
VLSI circuits for cryptographic authentication
Efficient quadratic placement of VLSI circuits
VLSI circuits for MIMO-OFDM physical layer
Design of VLSI circuits : based on VENUS
Routing congestion in VLSI circuits : estimation and optimization
Automated Design Error Debugging of Digital VLSI Circuits
The design of high-speed dynamic CMOS circuits for VLSI
Simulation-based analysis for NBTI degradation in combinational CMOS VLSI circuits
Programmable mixed-signal circuits
Modeling and suppressing unwanted parasitic interactions in superconducting circuits
Modeling and suppressing unwanted parasitic interactions in superconducting circuits
VLSI circuits for MIMO preprocessing
VLSI circuits for cryptographic authentication
Efficient quadratic placement of VLSI circuits
VLSI circuits for MIMO-OFDM physical layer
Design of VLSI circuits : based on VENUS
Routing congestion in VLSI circuits : estimation and optimization
Automated Design Error Debugging of Digital VLSI Circuits
The design of high-speed dynamic CMOS circuits for VLSI
Simulation-based analysis for NBTI degradation in combinational CMOS VLSI circuits
Programmable mixed-signal circuits
Modeling and suppressing unwanted parasitic interactions in superconducting circuits
Modeling and suppressing unwanted parasitic interactions in superconducting circuits
VLSI circuits for MIMO preprocessing
VLSI circuits for cryptographic authentication
Efficient quadratic placement of VLSI circuits
VLSI circuits for MIMO-OFDM physical layer
Design of VLSI circuits : based on VENUS
Routing congestion in VLSI circuits : estimation and optimization
Automated Design Error Debugging of Digital VLSI Circuits
The design of high-speed dynamic CMOS circuits for VLSI
Simulation-based analysis for NBTI degradation in combinational CMOS VLSI circuits
Programmable mixed-signal circuits
Modeling and suppressing unwanted parasitic interactions in superconducting circuits