Efficient Inter-Task Communication in Tiled Many-Core System-on-Chip Architectures
- Weitere Titel
-
Effiziente Inter-Task-Kommunikation in Tiled Many-Core System-on-Chip-Architekturen
- Standort
-
Deutsche Nationalbibliothek Frankfurt am Main
- Umfang
-
Online-Ressource
- Sprache
-
Englisch
- Anmerkungen
-
München, Technische Universität München, Dissertation, 2018
- Schlagwort
-
Communication
Hardware
- Ereignis
-
Veröffentlichung
- (wo)
-
München
- (wer)
-
Universitätsbibliothek der TU München
- (wann)
-
2018
- Urheber
-
Wallentowitz, Stefan
- Beteiligte Personen und Organisationen
-
Herkersdorf, Andreas
Gerndt, Hans Michael
- URN
-
urn:nbn:de:bvb:91-diss-20181008-1438539-1-1
- Rechteinformation
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Letzte Aktualisierung
-
15.08.2025, 07:31 MESZ
Datenpartner
Dieses Objekt wird bereitgestellt von:
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Beteiligte
- Wallentowitz, Stefan
- Herkersdorf, Andreas
- Gerndt, Hans Michael
- Universitätsbibliothek der TU München
Entstanden
- 2018
Ähnliche Objekte (12)
Scalable Task Schedulers for Many-Core Architectures
A Scalable and Adaptive Network on Chip for Many-Core Architectures
Communication infrastructure modeling of many-core architectures
Co-scheduling on Upcoming Many-Core Architectures
Communication Infrastructure Modeling of Many-Core Architectures
Exploiting many-core architectures for dimensionally adaptive sparse grids
Refactoring the UrQMD model for many-core architectures
Refactoring the UrQMD model for many-core architectures
A Modular Platform for Adaptive Heterogeneous Many-Core Architectures
Prototyping Methodologies and Design of Communication-centric Heterogeneous Many-core Architectures
High-level simulation of concurrency operations in microthreaded many-core architectures
Self-awareness in heterogeneous, adaptive many-core architectures enabling proactive, self-optimizing systems
Scalable Task Schedulers for Many-Core Architectures
A Scalable and Adaptive Network on Chip for Many-Core Architectures
Communication infrastructure modeling of many-core architectures
Co-scheduling on Upcoming Many-Core Architectures
Communication Infrastructure Modeling of Many-Core Architectures
Exploiting many-core architectures for dimensionally adaptive sparse grids
Refactoring the UrQMD model for many-core architectures
Refactoring the UrQMD model for many-core architectures
A Modular Platform for Adaptive Heterogeneous Many-Core Architectures
Prototyping Methodologies and Design of Communication-centric Heterogeneous Many-core Architectures
High-level simulation of concurrency operations in microthreaded many-core architectures
Self-awareness in heterogeneous, adaptive many-core architectures enabling proactive, self-optimizing systems
Scalable Task Schedulers for Many-Core Architectures
A Scalable and Adaptive Network on Chip for Many-Core Architectures
Communication infrastructure modeling of many-core architectures
Co-scheduling on Upcoming Many-Core Architectures
Communication Infrastructure Modeling of Many-Core Architectures
Exploiting many-core architectures for dimensionally adaptive sparse grids
Refactoring the UrQMD model for many-core architectures
Refactoring the UrQMD model for many-core architectures
A Modular Platform for Adaptive Heterogeneous Many-Core Architectures
Prototyping Methodologies and Design of Communication-centric Heterogeneous Many-core Architectures
High-level simulation of concurrency operations in microthreaded many-core architectures