Hochschulschrift
Communication Infrastructure Modeling of Many-Core Architectures
- Alternative title
-
Communication Infrastructure Modeling of Many-Core Architectures
- Location
-
Deutsche Nationalbibliothek Frankfurt am Main
- Extent
-
Online-Ressource
- Language
-
Englisch
- Notes
-
Darmstadt, Technische Universität Darmstadt, Dissertation, 2011
- Event
-
Veröffentlichung
- (where)
-
Darmstadt
- (who)
-
Universitäts- und Landesbibliothek Darmstadt
- (when)
-
2012
- Creator
- Contributor
-
Glesner, Manfred
Eveking, Hans
Klein, Anja
Soares Indrusiak, Leandro
Santini, Silvia
- URN
-
urn:nbn:de:tuda-tuprints-31212
- Rights
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
-
25.03.2025, 1:48 PM CET
Data provider
This object is provided by:
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Object type
- Hochschulschrift
Associated
- Möller, Leandro
- Glesner, Manfred
- Eveking, Hans
- Klein, Anja
- Soares Indrusiak, Leandro
- Santini, Silvia
- Universitäts- und Landesbibliothek Darmstadt
Time of origin
- 2012
Other Objects (12)
Communication infrastructure modeling of many-core architectures
Prototyping Methodologies and Design of Communication-centric Heterogeneous Many-core Architectures
Efficient Inter-Task Communication in Tiled Many-Core System-on-Chip Architectures
Co-scheduling on Upcoming Many-Core Architectures
Scalable Task Schedulers for Many-Core Architectures
Near-Memory Acceleration of Inter-Process Communication on Tile-Based Many-Core Architectures
Exploiting many-core architectures for dimensionally adaptive sparse grids
Refactoring the UrQMD model for many-core architectures
A Modular Platform for Adaptive Heterogeneous Many-Core Architectures
Refactoring the UrQMD model for many-core architectures
Effective communication methods for many core architectures with on chip networks in the absence of cache coherence
A Scalable and Adaptive Network on Chip for Many-Core Architectures
Communication infrastructure modeling of many-core architectures
Prototyping Methodologies and Design of Communication-centric Heterogeneous Many-core Architectures
Efficient Inter-Task Communication in Tiled Many-Core System-on-Chip Architectures
Co-scheduling on Upcoming Many-Core Architectures
Scalable Task Schedulers for Many-Core Architectures
Near-Memory Acceleration of Inter-Process Communication on Tile-Based Many-Core Architectures
Exploiting many-core architectures for dimensionally adaptive sparse grids
Refactoring the UrQMD model for many-core architectures
A Modular Platform for Adaptive Heterogeneous Many-Core Architectures
Refactoring the UrQMD model for many-core architectures
Effective communication methods for many core architectures with on chip networks in the absence of cache coherence
A Scalable and Adaptive Network on Chip for Many-Core Architectures
Communication infrastructure modeling of many-core architectures
Prototyping Methodologies and Design of Communication-centric Heterogeneous Many-core Architectures
Efficient Inter-Task Communication in Tiled Many-Core System-on-Chip Architectures
Co-scheduling on Upcoming Many-Core Architectures
Scalable Task Schedulers for Many-Core Architectures
Near-Memory Acceleration of Inter-Process Communication on Tile-Based Many-Core Architectures
Exploiting many-core architectures for dimensionally adaptive sparse grids
Refactoring the UrQMD model for many-core architectures
A Modular Platform for Adaptive Heterogeneous Many-Core Architectures
Refactoring the UrQMD model for many-core architectures
Effective communication methods for many core architectures with on chip networks in the absence of cache coherence