Hybrid CMOS-Memristor synapse circuits for implementing Ca ion-based plasticity model
- Location
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Deutsche Nationalbibliothek Frankfurt am Main
- Extent
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1 Online-Ressource.
- Language
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Englisch
- Bibliographic citation
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Hybrid CMOS-Memristor synapse circuits for implementing Ca ion-based plasticity model ; volume:14 ; number:1 ; day:2 ; month:8 ; year:2024 ; pages:1-14 ; date:12.2024
Scientific reports ; 14, Heft 1 (2.8.2024), 1-14, 12.2024
- Creator
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Lim, Jae Gwang
Park, Sung-jae
Lee, Sang Min
Jeong, Yeonjoo
Kim, Jaewook
Lee, Suyoun
Park, Jongkil
Hwang, Gyu Weon
Lee, Kyeong-Seok
Park, Seongsik
Jang, Hyun Jae
Ju, Byeong-Kwon
Park, Jong Keuk
Kim, Inho
- Contributor
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SpringerLink (Online service)
- DOI
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10.1038/s41598-024-68359-x
- URN
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urn:nbn:de:101:1-2411212220558.771393379927
- Rights
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Open Access; Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
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15.08.2025, 7:21 AM CEST
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Associated
- Lim, Jae Gwang
- Park, Sung-jae
- Lee, Sang Min
- Jeong, Yeonjoo
- Kim, Jaewook
- Lee, Suyoun
- Park, Jongkil
- Hwang, Gyu Weon
- Lee, Kyeong-Seok
- Park, Seongsik
- Jang, Hyun Jae
- Ju, Byeong-Kwon
- Park, Jong Keuk
- Kim, Inho
- SpringerLink (Online service)
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Author Correction: Hybrid CMOS-Memristor synapse circuits for implementing Ca ion-based plasticity model
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Author Correction: Hybrid CMOS-Memristor synapse circuits for implementing Ca ion-based plasticity model
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Back‐End‐of‐Line SiC‐Based Memristor for Resistive Memory and Artificial Synapse
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Author Correction: Hybrid CMOS-Memristor synapse circuits for implementing Ca ion-based plasticity model
CMOS-Compatible Memristor for Optoelectronic Neuromorphic Computing
Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design
Memristor crossbar architectures for implementing deep neural networks
Modelling and investigation of memristor devices, circuits, and systems
Terahertz Circuits and Systems in CMOS
Degradation Models and Optimizations for CMOS Circuits
Adiabatic circuits: converter for static CMOS signals
Proton‐Modulated Resistive Switching in a Synapse‐Like Tyrosine‐Rich Peptide‐Based Memristor
Back‐End‐of‐Line SiC‐Based Memristor for Resistive Memory and Artificial Synapse
CMOS circuits design and optimization for subretinal implants