- Location
-
Deutsche Nationalbibliothek Frankfurt am Main
- Extent
-
Online-Ressource
- Language
-
Englisch
- Bibliographic citation
-
Low Power High Speed Vedic Techniques in Recent VLSI Design – A Survey ; volume:4 ; number:6 ; year:2020 ; pages:147-156 ; September
Perspectives in Communication, Embedded-Systems and Signal-Processing (PiCES) ; 4, Heft 6 (2020), 147-156, September
- Classification
-
Elektrotechnik, Elektronik
- Creator
-
Dayanand, Swathi
K R, Varshitha
T, Rohini
Shirur, Yasha Jyothi M.
Munavalli, Jyoti R.
- Contributor
-
Department of ECE, BNMIT, Bangalore, India
- URN
-
urn:nbn:de:101:1-2020110519410031301404
- Rights
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
-
15.08.2025, 7:33 AM CEST
Data provider
This object is provided by:
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Associated
- Dayanand, Swathi
- K R, Varshitha
- T, Rohini
- Shirur, Yasha Jyothi M.
- Munavalli, Jyoti R.
- Department of ECE, BNMIT, Bangalore, India
Other Objects (12)
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Concurrent multipath power delay optimization for high speed digital VLSI systems
Low power VLSI design : fundamentals
Data statistics and low-power digital VLSI
The design of high-speed dynamic CMOS circuits for VLSI
LowPower-Design-Methoden für VLSI-CMOS-Digitalschaltungen
High-speed pulse techniques
VLSI-Systeme
VLSI-Systeme
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Stufungsbeurteilung DEERE "15 Speed Power Shift"; speed spacing check DEERE "15 Speed Power Shift"
Power efficiency and the mapping of communication algorithms into VLSI
Low-power techniques for low-frequency VLSI applications
Concurrent multipath power delay optimization for high speed digital VLSI systems
Low power VLSI design : fundamentals
Data statistics and low-power digital VLSI
The design of high-speed dynamic CMOS circuits for VLSI
LowPower-Design-Methoden für VLSI-CMOS-Digitalschaltungen
High-speed pulse techniques
VLSI-Systeme
VLSI-Systeme
VLSI-Komplexitätsuntersuchungen
Stufungsbeurteilung DEERE "15 Speed Power Shift"; speed spacing check DEERE "15 Speed Power Shift"
Power efficiency and the mapping of communication algorithms into VLSI
Low-power techniques for low-frequency VLSI applications
Concurrent multipath power delay optimization for high speed digital VLSI systems
Low power VLSI design : fundamentals
Data statistics and low-power digital VLSI
The design of high-speed dynamic CMOS circuits for VLSI
LowPower-Design-Methoden für VLSI-CMOS-Digitalschaltungen
High-speed pulse techniques
VLSI-Systeme
VLSI-Systeme
VLSI-Komplexitätsuntersuchungen
Stufungsbeurteilung DEERE "15 Speed Power Shift"; speed spacing check DEERE "15 Speed Power Shift"