- Location
-
Deutsche Nationalbibliothek Frankfurt am Main
- Extent
-
Online-Ressource
- Language
-
Englisch
- Notes
-
In: Architecture of Computing Systems - ARCS 2017. Wien, 03.-06. April 2017
- Event
-
Veröffentlichung
- (where)
-
Dresden
- (who)
-
Technische Universität Dresden
- (when)
-
2023
- Creator
-
Arega, Frehiwot Melak
Hähnel, Markus
Dargie, Waltenegus
- URN
-
urn:nbn:de:bsz:14-qucosa2-854632
- Rights
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
-
25.03.2025, 1:53 PM CET
Data provider
This object is provided by:
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Associated
- Arega, Frehiwot Melak
- Hähnel, Markus
- Dargie, Waltenegus
- Technische Universität Dresden
Time of origin
- 2023
Other Objects (12)
KAVUAKA: A Low-Power Application-Specific Processor Architecture for Digital Hearing Aids
A Reconfigurable Processor for Heterogeneous Multi-Core Architectures
Algorithm architecture trade offs in network processor design
Optimal global instruction scheduling for the Itanium processor architecture
Optimal global instruction scheduling for the Itanium processor architecture
Efficient and flexible cryptographic co-processor architecture for server application
Cryptonite : a programmable crypto processor architecture for high bandwidth applications
Cryptonite : a programmable crypto processor architecture for high bandwidth applications
Processor frequency sweet spot prediction based on dynamic code analysis
IBM PowerNP Network Processor : hardware, software and applications
Processor architecture : from dataflow to superscalar and beyond ; with 34 tables
A network processor architecture for high speed carrier grade ethernet networks
KAVUAKA: A Low-Power Application-Specific Processor Architecture for Digital Hearing Aids
A Reconfigurable Processor for Heterogeneous Multi-Core Architectures
Algorithm architecture trade offs in network processor design
Optimal global instruction scheduling for the Itanium processor architecture
Optimal global instruction scheduling for the Itanium processor architecture
Efficient and flexible cryptographic co-processor architecture for server application
Cryptonite : a programmable crypto processor architecture for high bandwidth applications
Cryptonite : a programmable crypto processor architecture for high bandwidth applications
Processor frequency sweet spot prediction based on dynamic code analysis
IBM PowerNP Network Processor : hardware, software and applications
Processor architecture : from dataflow to superscalar and beyond ; with 34 tables
A network processor architecture for high speed carrier grade ethernet networks
KAVUAKA: A Low-Power Application-Specific Processor Architecture for Digital Hearing Aids
A Reconfigurable Processor for Heterogeneous Multi-Core Architectures
Algorithm architecture trade offs in network processor design
Optimal global instruction scheduling for the Itanium processor architecture
Optimal global instruction scheduling for the Itanium processor architecture
Efficient and flexible cryptographic co-processor architecture for server application
Cryptonite : a programmable crypto processor architecture for high bandwidth applications
Cryptonite : a programmable crypto processor architecture for high bandwidth applications
Processor frequency sweet spot prediction based on dynamic code analysis
IBM PowerNP Network Processor : hardware, software and applications
Processor architecture : from dataflow to superscalar and beyond ; with 34 tables