Design and Programming Methods for Reconfigurable Multi-Core Architectures using a Network-on-Chip-Centric Approach
- Standort
-
Deutsche Nationalbibliothek Frankfurt am Main
- Umfang
-
Online-Ressource
- Sprache
-
Englisch
- Anmerkungen
-
Dresden, Technische Universität Dresden, Dissertation, 2021
- Klassifikation
-
Elektrotechnik, Elektronik
- Schlagwort
-
Design
Asir
- Ereignis
-
Veröffentlichung
- (wo)
-
Dresden
- (wer)
-
Technische Universität Dresden
- (wann)
-
2022
- Urheber
- Beteiligte Personen und Organisationen
- URN
-
urn:nbn:de:bsz:14-qucosa2-798707
- Rechteinformation
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Letzte Aktualisierung
-
25.03.2025, 13:49 MEZ
Datenpartner
Dieses Objekt wird bereitgestellt von:
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Beteiligte
- Rettkowski, Jens
- Stroobandt, Dirk
- Göhringer, Diana
- Technische Universität Dresden
Entstanden
- 2022
Ähnliche Objekte (12)
A Reconfigurable Processor for Heterogeneous Multi-Core Architectures
Abstractions for performance programming on multi-core architectures with hierarchial memory
Abstractions for Performance Programming on Multi-Core Architectures with Hierarchical Memory
Dynamic coarse grained reconfigurable architectures
Dynamically reconfigurable architectures : 22.02.1998 - 27.02.1998
Query processing on multi-core architectures
Object-oriented development for reconfigurable architectures
Bitonic Sorting on Dynamically Reconfigurable Architectures
Predictable and high performance multi-core architectures
Network Coding Strategies for Multi-Core Architectures
Network coding strategies for multi-core architectures
Trustworthy reconfigurable systems : enhancing the security capabilities of reconfigurable hardware architectures
A Reconfigurable Processor for Heterogeneous Multi-Core Architectures
Abstractions for performance programming on multi-core architectures with hierarchial memory
Abstractions for Performance Programming on Multi-Core Architectures with Hierarchical Memory
Dynamic coarse grained reconfigurable architectures
Dynamically reconfigurable architectures : 22.02.1998 - 27.02.1998
Query processing on multi-core architectures
Object-oriented development for reconfigurable architectures
Bitonic Sorting on Dynamically Reconfigurable Architectures
Predictable and high performance multi-core architectures
Network Coding Strategies for Multi-Core Architectures
Network coding strategies for multi-core architectures
Trustworthy reconfigurable systems : enhancing the security capabilities of reconfigurable hardware architectures
A Reconfigurable Processor for Heterogeneous Multi-Core Architectures
Abstractions for performance programming on multi-core architectures with hierarchial memory
Abstractions for Performance Programming on Multi-Core Architectures with Hierarchical Memory
Dynamic coarse grained reconfigurable architectures
Dynamically reconfigurable architectures : 22.02.1998 - 27.02.1998
Query processing on multi-core architectures
Object-oriented development for reconfigurable architectures
Bitonic Sorting on Dynamically Reconfigurable Architectures
Predictable and high performance multi-core architectures
Network Coding Strategies for Multi-Core Architectures
Network coding strategies for multi-core architectures