Hochschulschrift
Abstractions for Performance Programming on Multi-Core Architectures with Hierarchical Memory
- Alternative title
-
Abstraktionen zur performanten Programmierung von Multi-Core Architekturen mit hierarchischem Speicher
- Location
-
Deutsche Nationalbibliothek Frankfurt am Main
- Extent
-
Online-Ressource
- Language
-
Englisch
- Notes
-
In: Aachen : Apprimus Verlag, 2016
RWTH Aachen University, Dissertation, 2016
- Bibliographic citation
-
Ergebnisse aus der Informatik ; 7
- Keyword
-
Mehrkernprozessor
Speicherhierarchie
Gemeinsamer Speicher
Parallelverarbeitung
Programmierung
Abstraktionsebene
Mehrprozessorsystem
NUMA-Architektur
OpenMP
- Event
-
Veröffentlichung
- (where)
-
Aachen
- (who)
-
Universitätsbibliothek der RWTH Aachen
- (when)
-
2016
- Creator
- Contributor
-
Müller, Mathias S.
Bischof, Christian
Chapman, Barbara
- URN
-
urn:nbn:de:hbz:82-rwth-2016-062610
- Rights
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
- 15.08.2025, 7:20 AM CEST
Data provider
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Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Object type
- Hochschulschrift
Associated
- Terboven, Christian
- Müller, Mathias S.
- Bischof, Christian
- Chapman, Barbara
- Universitätsbibliothek der RWTH Aachen
Time of origin
- 2016
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Abstractions for performance programming on multi-core architectures with hierarchial memory
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Network coding strategies for multi-core architectures
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Predictable and high performance multi-core architectures
A Reconfigurable Processor for Heterogeneous Multi-Core Architectures
Design and Programming Methods for Reconfigurable Multi-Core Architectures using a Network-on-Chip-Centric Approach
A practical programming model for the multi-core era : proceedings
Analysis and simulation of scheduling techniques for real-time embedded multi-core architectures
Strategies to parallelize a finite element mesh truncation technique on multi-core and many-core architectures
Provably sound semantics stack for multi-core system programming with kernel threads
Multi-core symbolic bisimulation minimisation
Abstractions for performance programming on multi-core architectures with hierarchial memory
Query processing on multi-core architectures
Network coding strategies for multi-core architectures
Network Coding Strategies for Multi-Core Architectures
Predictable and high performance multi-core architectures
A Reconfigurable Processor for Heterogeneous Multi-Core Architectures
Design and Programming Methods for Reconfigurable Multi-Core Architectures using a Network-on-Chip-Centric Approach
A practical programming model for the multi-core era : proceedings
Analysis and simulation of scheduling techniques for real-time embedded multi-core architectures
Strategies to parallelize a finite element mesh truncation technique on multi-core and many-core architectures
Provably sound semantics stack for multi-core system programming with kernel threads