Evict+Spec+Time: Exploiting Out-of-Order Execution to Improve Cache-Timing Attacks
Abstract: Speculative out-of-order execution is a strategy of masking execution latency by allowing younger instructions to execute before older instructions. While originally considered to be innocuous, speculative out-of-order execution was brought into the spotlight with the 2018 publication of the Spectre and Meltdown attacks. These attacks demonstrated that microarchitectural side channels can leak sensitive data accessed by speculatively executed instructions that are not part of the normal program execution. Since then, a significant effort has been vested in investigating how microarchitectural side channels can leak data from speculatively executed instructions and how to control this leakage. However, much less is known about how speculative out-of-order execution affects microarchitectural side-channel attacks. In this paper, we investigate how speculative out-of-order execution affects the Evict+Time cache attack. Evict+Time is based on the observation that cache misses are slowe.... https://tches.iacr.org/index.php/TCHES/article/view/11676
- Location
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Deutsche Nationalbibliothek Frankfurt am Main
- Extent
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Online-Ressource
- Language
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Englisch
- Bibliographic citation
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Evict+Spec+Time: Exploiting Out-of-Order Execution to Improve Cache-Timing Attacks ; volume:2024 ; number:3 ; year:2024
IACR transactions on cryptographic hardware and embedded systems ; 2024, Heft 3 (2024)
- Creator
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Cheng, Shing Hing William
Chuengsatiansup, Chitchanok
Genkin, Daniel
McNeil, Dallas
Murray, Toby
Yarom, Yuval
Zhang, Zhiyuan
- DOI
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10.46586/tches.v2024.i3.224-248
- URN
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urn:nbn:de:101:1-2407241855559.397142139866
- Rights
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Open Access; Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
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14.08.2025, 11:01 AM CEST
Data provider
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Associated
- Cheng, Shing Hing William
- Chuengsatiansup, Chitchanok
- Genkin, Daniel
- McNeil, Dallas
- Murray, Toby
- Yarom, Yuval
- Zhang, Zhiyuan
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Cache-Timing Attack Against HQC
CacheQuote:efficiently recovering long-term secrets of SGX EPID via cache attacks
Timing attacks and local timing attacks against Barrett’s modular multiplication algorithm
Generalizing Timing Predictions to Set-Associative Caches
Microarchitectural Attacks on Trusted Execution Environments
Practical Cache Attacks from the Network and Bad Cat Puns
ASLR on the line: Practical cache attacks on the MMU
Malware Guard Extension: abusing Intel SGX to conceal cache attacks
Keep the PokerFace on! Thwarting cache side channel attacks by memory bus monitoring and cache obfuscation
Cache-cache
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Cache-timing attacks on RSA key generation
Cache-Timing Attack Against HQC
CacheQuote:efficiently recovering long-term secrets of SGX EPID via cache attacks
Timing attacks and local timing attacks against Barrett’s modular multiplication algorithm
Generalizing Timing Predictions to Set-Associative Caches
Microarchitectural Attacks on Trusted Execution Environments
Practical Cache Attacks from the Network and Bad Cat Puns
ASLR on the line: Practical cache attacks on the MMU
Malware Guard Extension: abusing Intel SGX to conceal cache attacks
Keep the PokerFace on! Thwarting cache side channel attacks by memory bus monitoring and cache obfuscation
Cache-cache