Hochschulschrift
Accurate power analysis of integrated CMOS circuits on gate level
- Location
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Deutsche Nationalbibliothek Frankfurt am Main
- Dimensions
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30 cm
- Extent
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VI, 145 S.
- Language
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Englisch
- Notes
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graph. Darst.
Oldenburg, Univ., Diss., 2001 (Nicht für den Austausch)
- Keyword
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CMOS
Gattersimulation
Leistungsbedarf
Glitch
- Creator
- Table of contents
- Rights
-
Bei diesem Objekt liegt nur das Inhaltsverzeichnis digital vor. Der Zugriff darauf ist unbeschränkt möglich.
- Last update
-
11.03.2025, 11:47 AM CET
Data provider
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Object type
- Hochschulschrift
Associated
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