Masking Floating-Point Number Multiplication and Addition of Falcon : First- and Higher-order Implementations and Evaluations

Abstract: In this paper, we provide the first masking scheme for floating-point number multiplication and addition to defend against recent side-channel attacks on Falcon’s pre-image vector computation. Our approach involves a masked nonzero check gadget that securely identifies whether a shared value is zero. This gadget can be utilized for various computations such as rounding the mantissa, computing the sticky bit, checking the equality of two values, and normalizing a number. To support the masked floating-point number addition, we also developed a masked shift and a masked normalization gadget. Our masking design provides both first- and higherorder mask protection, and we demonstrate the theoretical security by proving the (Strong)-Non-Interference properties in the probing model. To evaluate the performance of our approach, we implemented unmasked, first-order, and second-order algorithms on an Arm Cortex-M4 processor, providing cycle counts and the number of random bytes used. We als.... https://tches.iacr.org/index.php/TCHES/article/view/11428

Angaben zum Objekt

• Standort: Deutsche Nationalbibliothek Frankfurt am Main
• Umfang: Online-Ressource
• Sprache: Englisch

Verweise und Beziehungen

• Erschienen in: Masking Floating-Point Number Multiplication and Addition of Falcon ; volume:2024 ; number:2 ; year:2024 ; IACR transactions on cryptographic hardware and embedded systems ; 2024, Heft 2 (2024)

Beteiligte, Orts- und Zeitangaben

• Urheber: Chen, Keng-Yu ; Chen, Jiun-Peng

Weitere Informationen

• DOI: 10.46586/tches.v2024.i2.276-303
• URN: urn:nbn:de:101:1-2024032018000086634691
• Rechteinformation: Open Access; Der Zugriff auf das Objekt ist unbeschränkt möglich.
• Letzte Aktualisierung: 14.08.2025, 11:01 MESZ