Hochschulschrift
Worst case execution time estimation for advanced processor architectures
- Location
-
Deutsche Nationalbibliothek Frankfurt am Main
- Dimensions
-
30 cm
- Extent
-
VI, 142 S.
- Language
-
Englisch
- Notes
-
graph. Darst.
München, Techn. Univ., Diss., 2002 (Nicht für den Austausch)
- Keyword
-
Athlon
Worst-Case-Laufzeit
Laufzeitmessung
Echtzeitsystem
Extremwertstatistik
Pentium III
Worst-Case-Laufzeit
Laufzeitmessung
Echtzeitsystem
Extremwertstatistik
- Creator
- Table of contents
- Rights
-
Bei diesem Objekt liegt nur das Inhaltsverzeichnis digital vor. Der Zugriff darauf ist unbeschränkt möglich.
- Last update
-
11.03.2025, 11:49 AM CET
Data provider
This object is provided by:
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Object type
- Hochschulschrift
Associated
Other Objects (12)
Worst case execution time estimation for advanced processor architectures
Worst-Case Execution Time Guarantees for Runtime-Reconfigurable Architectures
Parallel processor architectures for image processing
Processor management in two-dimensional grid architectures
Symbolic worst case execution times
A Reconfigurable Processor for Heterogeneous Multi-Core Architectures
Generalized database index structures on massively parallel processor architectures
Embedded processor design challenges : systems, architectures, modeling, and simulation - SAMOS
Design of the Secure Execution PUF-based Processor (SEPP)
Stepwise transformation of algorithms into array processor architectures by the decomp
A Survey on Application Specific Processor Architectures for Digital Hearing Aids
14th International Workshop on Worst-Case Execution Time Analysis
Worst case execution time estimation for advanced processor architectures
Worst-Case Execution Time Guarantees for Runtime-Reconfigurable Architectures
Parallel processor architectures for image processing
Processor management in two-dimensional grid architectures
Symbolic worst case execution times
A Reconfigurable Processor for Heterogeneous Multi-Core Architectures
Generalized database index structures on massively parallel processor architectures
Embedded processor design challenges : systems, architectures, modeling, and simulation - SAMOS
Design of the Secure Execution PUF-based Processor (SEPP)
Stepwise transformation of algorithms into array processor architectures by the decomp
A Survey on Application Specific Processor Architectures for Digital Hearing Aids
14th International Workshop on Worst-Case Execution Time Analysis
Worst case execution time estimation for advanced processor architectures
Worst-Case Execution Time Guarantees for Runtime-Reconfigurable Architectures
Parallel processor architectures for image processing
Processor management in two-dimensional grid architectures
Symbolic worst case execution times
A Reconfigurable Processor for Heterogeneous Multi-Core Architectures
Generalized database index structures on massively parallel processor architectures
Embedded processor design challenges : systems, architectures, modeling, and simulation - SAMOS
Design of the Secure Execution PUF-based Processor (SEPP)
Stepwise transformation of algorithms into array processor architectures by the decomp
A Survey on Application Specific Processor Architectures for Digital Hearing Aids