High-speed instruction-set coprocessor for lattice-based key encapsulation mechanism: Saber in hardware
- Location
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Deutsche Nationalbibliothek Frankfurt am Main
- Extent
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Online-Ressource
- Language
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Englisch
- Bibliographic citation
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High-speed instruction-set coprocessor for lattice-based key encapsulation mechanism: Saber in hardware ; volume:2020 ; number:4 ; pages:443-466
IACR transactions on cryptographic hardware and embedded systems ; 2020, Heft 4, 443-466
- Classification
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Informatik
- Creator
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Sinha Roy, Sujoy
Basso, Andrea
- DOI
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10.13154/tches.v2020.i4.443-466
- URN
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urn:nbn:de:hbz:294-TCHES-1503
- Rights
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Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
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15.08.2025, 7:23 AM CEST
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Associated
- Sinha Roy, Sujoy
- Basso, Andrea
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Standard lattice-based key encapsulation on embedded devices
Computing Shortest Lattice Vectors on Special Hardware
High-speed masking for polynomial comparison in lattice-based KEMs
Verified NTT multiplications for NISTPQC KEM lattice finalists: Kyber, SABER, and NTRU
High-speed hardware architecture for implementations of multivariate signature generations on FPGAs
Hardware-effiziente, hochparallele Implementierungen von Lattice-Boltzmann-Verfahren für komplexe Geometrien
Sabiduría. - Saber
Del saber
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Standard lattice-based key encapsulation on embedded devices
Computing Shortest Lattice Vectors on Special Hardware
High-speed masking for polynomial comparison in lattice-based KEMs
Verified NTT multiplications for NISTPQC KEM lattice finalists: Kyber, SABER, and NTRU
High-speed hardware architecture for implementations of multivariate signature generations on FPGAs
Hardware-effiziente, hochparallele Implementierungen von Lattice-Boltzmann-Verfahren für komplexe Geometrien
Sabiduría. - Saber
Del saber
Para saber
Para saber
¿Cómo saber?