A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic

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Location: Deutsche Nationalbibliothek Frankfurt am Main

Extent: Online-Ressource

Language: Englisch

Bibliographic citation: In: IEEE Transactions on Circuits and Systems I: Regular Papers (2021): [Early Access].

Event: Veröffentlichung

(where): Erlangen

(who): Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)

(when): 2021

Creator: Lakshmi, Vijaya
Reuben, John
Pudi, Vikramkumar

DOI: 10.1109/TCSI.2021.3129827

URN: urn:nbn:de:bvb:29-opus4-179530

Rights: Der Zugriff auf das Objekt ist unbeschränkt möglich.

Last update: 15.08.2025, 7:22 AM CEST

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Associated

Lakshmi, Vijaya
Reuben, John
Pudi, Vikramkumar
Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)

Time of origin

2021

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A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic

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Other Objects (12)

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

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Typed semigroups, majority logic, and threshold circuits

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Design of a Quaternary Component and Wallace Tree Integrated Baugh-Wooley Multiplier

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Design of a Quaternary Component and Wallace Tree Integrated Baugh-Wooley Multiplier

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Majority

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