Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes

Location
Deutsche Nationalbibliothek Frankfurt am Main
ISSN
2523-3971
Extent
Online-Ressource
Language
Englisch
Notes
online resource.

Bibliographic citation
Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes ; volume:3 ; number:5 ; day:7 ; month:4 ; year:2021 ; pages:1-13 ; date:5.2021
SN applied sciences ; 3, Heft 5 (7.4.2021), 1-13, 5.2021

Creator
Mohapatra, E.
Dash, T. P.
Jena, J.
Das, S.
Maiti, C. K.
Contributor
SpringerLink (Online service)

DOI
10.1007/s42452-021-04539-y
URN
urn:nbn:de:101:1-2021052908341879139291
Rights
Open Access; Der Zugriff auf das Objekt ist unbeschränkt möglich.
Last update
14.08.2025, 11:00 AM CEST

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Associated

  • Mohapatra, E.
  • Dash, T. P.
  • Jena, J.
  • Das, S.
  • Maiti, C. K.
  • SpringerLink (Online service)

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