Hochschulschrift
Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain
- Standort
-
Deutsche Nationalbibliothek Frankfurt am Main
- Maße
-
21 cm
- Umfang
-
141 Seiten
- Sprache
-
Englisch
- Anmerkungen
-
Illustrationen, Diagramme
Universität Stuttgart, Dissertation, 2019
- Klassifikation
-
Informatik
- Schlagwort
-
Decoder
Architektur
Code
Hardware
Leistungsbewertung
- Inhaltsverzeichnis
- Rechteinformation
-
Bei diesem Objekt liegt nur das Inhaltsverzeichnis digital vor. Der Zugriff darauf ist unbeschränkt möglich.
- Letzte Aktualisierung
-
11.03.2025, 12:13 MEZ
Datenpartner
Dieses Objekt wird bereitgestellt von:
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Objekttyp
- Hochschulschrift
Beteiligte
Entstanden
- 2019
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