A Deep Analysis of two Glitch-Free Hardware Masking Schemes SESYM and LMDPL

Abstract: In the context of masking, which is the dominant technique for protecting cryptographic hardware designs against Side-Channel Analysis (SCA) attacks, the focus has long been on the design of masking schemes that guarantee provable security in the presence of glitches. Unfortunately, achieving this comes at the cost of increased latency, since registers are required to stop glitch propagation. Previous work has attempted to reduce latency by eliminating registers, but the exponential increase in area makes such approaches impractical. Some relatively new attempts have used Dual-Rail Pre-charge (DRP) logic styles to avoid glitches in algorithmically masked circuits. Promising approaches in this area include LUT-based Masked Dual-Rail with Pre-charge Logic (LMDPL) and Self-Synchronized Masking (SESYM), presented at CHES 2020 and CHES 2022 respectively. Both schemes allow masking of arbitrary functions with only one cycle latency. However, even if glitches no longer occur, there are ot.... https://tches.iacr.org/index.php/TCHES/article/view/11670

Object Details

• Location: Deutsche Nationalbibliothek Frankfurt am Main
• Extent: Online-Ressource
• Language: Englisch

References and Relationships

• Bibliographic citation: A Deep Analysis of two Glitch-Free Hardware Masking Schemes SESYM and LMDPL ; volume:2024 ; number:3 ; year:2024 ; IACR transactions on cryptographic hardware and embedded systems ; 2024, Heft 3 (2024)

Contributors, Places and Time

• Creator: Müller, Nicolai ; Lammers, Daniel ; Moradi, Amir

Further information

• DOI: 10.46586/tches.v2024.i3.76-98
• URN: urn:nbn:de:101:1-2407241856294.122651592921
• Rights: Open Access; Der Zugriff auf das Objekt ist unbeschränkt möglich.
• Last update: 14.08.2025, 10:52 AM CEST