Impact of Reduced Gate‐to‐Source Spacing on Indium Phosphide High Electron Mobility Transistor Performance
- Standort
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Deutsche Nationalbibliothek Frankfurt am Main
- Umfang
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Online-Ressource
- Sprache
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Englisch
- Erschienen in
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Impact of Reduced Gate‐to‐Source Spacing on Indium Phosphide High Electron Mobility Transistor Performance ; volume:218 ; number:3 ; year:2021
Physica status solidi / A. A, Applications and materials science ; 218, Heft 3 (2021)
- Urheber
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Calvo Ruiz, Diego
Han, Daxin
Bonomo, Giorgio
Saranovac, Tamara
Ostinelli, Olivier
Bolognesi, Colombo R.
- DOI
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10.1002/pssa.202000191
- URN
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urn:nbn:de:101:1-2021031314433947797361
- Rechteinformation
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Open Access; Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Letzte Aktualisierung
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15.08.2025, 07:31 MESZ
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Beteiligte
- Calvo Ruiz, Diego
- Han, Daxin
- Bonomo, Giorgio
- Saranovac, Tamara
- Ostinelli, Olivier
- Bolognesi, Colombo R.
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Physics-Based Technology Computer-Aided Design and Compact Modeling with Special Emphasis on Advanced Indium-Phosphide Heterojunction Bipolar Transistors
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