Work-in-progress: design-space exploration of multi-core processors for safety-critical real-time systems
- Standort
-
Deutsche Nationalbibliothek Frankfurt am Main
- Umfang
-
Online-Ressource
- Sprache
-
Englisch
- Anmerkungen
-
In: 2017 IEEE Real-Time Systems Symposium (RTSS), 5-8 December 2017, Paris, France, S. 360-362
- Klassifikation
-
Informatik
- Ereignis
-
Veröffentlichung
- (wo)
-
Augsburg
- (wer)
-
Universität Augsburg
- (wann)
-
2017
- Ereignis
-
Veröffentlichung
- (wo)
-
Piscataway, NJ
- (wer)
-
IEEE
- (wann)
-
2017
- Urheber
- Beteiligte Personen und Organisationen
-
Mueller, Frank
Puaut, Isabelle
- DOI
-
10.1109/rtss.2017.00040
- URN
-
urn:nbn:de:bvb:384-opus4-697831
- Rechteinformation
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Letzte Aktualisierung
-
14.08.2025, 10:59 MESZ
Datenpartner
Dieses Objekt wird bereitgestellt von:
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Beteiligte
- Sapra, Dolly
- Altmeyer, Sebastian
- Mueller, Frank
- Puaut, Isabelle
- Universität Augsburg
- IEEE
Entstanden
- 2017
Ähnliche Objekte (12)
Schedulability analysis of non-preemptive real-time scheduling for multicore processors with shared caches
Precise WCET calculation in highly variant real-time systems
A new notion of useful cache block to improve the bounds of cache-related preemption delay
Mixed criticality systems with varying context switch costs
A model-based development environment for rapid-prototyping of latency-sensitive automotive control software
Schedulability analysis of global scheduling for multicore systems with shared caches
Fast and precise cache performance estimation for out-of-order execution
Stack memory requirements of AUTOSAR/OSEK-compliant scheduling policies
Schedulability using native non-preemptive groups on an AUTOSAR/OSEK platform with caches
Cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems
Towards energy-, time- and security-aware multi-core coordination
30th Euromicro Conference on Real-Time Systems: ECRTS 2018, July 3–6, 2018, Barcelona, Spain
Schedulability analysis of non-preemptive real-time scheduling for multicore processors with shared caches
Precise WCET calculation in highly variant real-time systems
A new notion of useful cache block to improve the bounds of cache-related preemption delay
Mixed criticality systems with varying context switch costs
A model-based development environment for rapid-prototyping of latency-sensitive automotive control software
Schedulability analysis of global scheduling for multicore systems with shared caches
Fast and precise cache performance estimation for out-of-order execution
Stack memory requirements of AUTOSAR/OSEK-compliant scheduling policies
Schedulability using native non-preemptive groups on an AUTOSAR/OSEK platform with caches
Cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems
Towards energy-, time- and security-aware multi-core coordination
30th Euromicro Conference on Real-Time Systems: ECRTS 2018, July 3–6, 2018, Barcelona, Spain
Schedulability analysis of non-preemptive real-time scheduling for multicore processors with shared caches
Precise WCET calculation in highly variant real-time systems
A new notion of useful cache block to improve the bounds of cache-related preemption delay
Mixed criticality systems with varying context switch costs
A model-based development environment for rapid-prototyping of latency-sensitive automotive control software
Schedulability analysis of global scheduling for multicore systems with shared caches
Fast and precise cache performance estimation for out-of-order execution
Stack memory requirements of AUTOSAR/OSEK-compliant scheduling policies
Schedulability using native non-preemptive groups on an AUTOSAR/OSEK platform with caches
Cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems
Towards energy-, time- and security-aware multi-core coordination