Hierarchical Verification and Hierarchical Synthesis of the Power-Down Mode of Analog Circuits
- Weitere Titel
-
Hierarchische Verifikation und hierarchische Synthese des Power-Down-Modus analoger Schaltungen
- Standort
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Deutsche Nationalbibliothek Frankfurt am Main
- Umfang
-
Online-Ressource
- Sprache
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Englisch
- Anmerkungen
-
München, Technische Universität München, Dissertation, 2023
- Klassifikation
-
Elektrotechnik, Elektronik
- Schlagwort
-
Entwurfsautomation
Analoge integrierte Schaltung
Schaltungsanalyse
Analogschaltung
- Ereignis
-
Veröffentlichung
- (wo)
-
München
- (wer)
-
Universitätsbibliothek der TU München
- (wann)
-
2023
- Urheber
-
Neuner, Maximilian Ulrich
- Beteiligte Personen und Organisationen
- URN
-
urn:nbn:de:bvb:91-diss-20231207-1706307-1-5
- Rechteinformation
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Letzte Aktualisierung
-
15.08.2025, 07:20 MESZ
Datenpartner
Dieses Objekt wird bereitgestellt von:
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Beteiligte
- Neuner, Maximilian Ulrich
- Gräb, Helmut
- Sapatnekar, Sachin
- Paul, Steffen
- Universitätsbibliothek der TU München
Entstanden
- 2023
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