Hochschulschrift
Retargetable processor system integration into multi-processor system on chip platforms
- Location
-
Deutsche Nationalbibliothek Frankfurt am Main
- ISBN
-
9781402085741
- Dimensions
-
24 cm
- Extent
-
XIV, 162 S.
- Language
-
Englisch
- Notes
-
graph. Darst.
Zugl.: Aachen, Techn. Hochsch., Diss., A. Wieferink, 2007
- Classification
-
Elektrotechnik, Elektronik
- Keyword
-
System-on-Chip
Mehrprozessorsystem
Entwurfsautomation
System-on-Chip
Mehrprozessorsystem
Systemplattform
- Event
-
Veröffentlichung
- (where)
-
[Dordrecht]
- (who)
-
Springer
- (when)
-
2008
- Creator
- Table of contents
- Rights
-
Bei diesem Objekt liegt nur das Inhaltsverzeichnis digital vor. Der Zugriff darauf ist unbeschränkt möglich.
- Last update
-
11.03.2025, 12:18 PM CET
Data provider
This object is provided by:
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Object type
- Hochschulschrift
Associated
- Wieferink, Andreas
- Meyr, Heinrich
- Leupers, Rainer
- Springer
Time of origin
- 2008
Other Objects (12)
Integrated system level modeling of network on chip enabled multi-processor platforms
KEP2 (Kiel Esterel Processor 2) THE ESTEREL PROCESSOR
Predicting cache contention in multicore processor systems
The Kiel Esterel processor : a multi-threaded reactive processor
High-level estimation and exploration of reliability for multi-processor system-on-chip
Final System-Level Software for the MERASA Processor
Throughput analysis for processor systems with cache hierarchies
MIKROPLIS : a textbank management system and idea processor
The Kiel Esterel processor - a semi-custom, configurable reactive processor
Efficient and predictable thread synchronization mechanisms for mixed-criticality systems on shared-memory multi-processor platforms
Liesegang processor syn 1
A scalable quantum processor
Integrated system level modeling of network on chip enabled multi-processor platforms
KEP2 (Kiel Esterel Processor 2) THE ESTEREL PROCESSOR
Predicting cache contention in multicore processor systems
The Kiel Esterel processor : a multi-threaded reactive processor
High-level estimation and exploration of reliability for multi-processor system-on-chip
Final System-Level Software for the MERASA Processor
Throughput analysis for processor systems with cache hierarchies
MIKROPLIS : a textbank management system and idea processor
The Kiel Esterel processor - a semi-custom, configurable reactive processor
Efficient and predictable thread synchronization mechanisms for mixed-criticality systems on shared-memory multi-processor platforms
Liesegang processor syn 1
A scalable quantum processor
Integrated system level modeling of network on chip enabled multi-processor platforms
KEP2 (Kiel Esterel Processor 2) THE ESTEREL PROCESSOR
Predicting cache contention in multicore processor systems
The Kiel Esterel processor : a multi-threaded reactive processor
High-level estimation and exploration of reliability for multi-processor system-on-chip
Final System-Level Software for the MERASA Processor
Throughput analysis for processor systems with cache hierarchies
MIKROPLIS : a textbank management system and idea processor
The Kiel Esterel processor - a semi-custom, configurable reactive processor
Efficient and predictable thread synchronization mechanisms for mixed-criticality systems on shared-memory multi-processor platforms
Liesegang processor syn 1