Hochschulschrift
Architecture design for distributed mixed-criticality systems based on multi-core chips
- Location
-
Deutsche Nationalbibliothek Frankfurt am Main
- Extent
-
Online-Ressource
- Language
-
Englisch
- Notes
-
Siegen, Universität Siegen, Dissertation, 2017
- Classification
-
Architektur
- Keyword
-
Netzwerktopologie ; Sicherheitskritisches System ; Mehrkernprozessor ; Scheduling ; Zeitgesteuertes System
- Event
-
Veröffentlichung
- (where)
-
Siegen
- (who)
-
Universitätsbibliothek der Universität Siegen
- (when)
-
2017
- Creator
- URN
-
urn:nbn:de:hbz:467-11314
- Rights
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
-
15.08.2025, 7:29 AM CEST
Data provider
This object is provided by:
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Object type
- Hochschulschrift
Associated
- Abuteir, Mohammed
- Universitätsbibliothek der Universität Siegen
Time of origin
- 2017
Other Objects (12)
Analysis of Inter-Chip Communication Patterns on Multi-Core Distributed Shared-Memory Computers
Multi-core symbolic bisimulation minimisation
parMERASA Multi-core RTOS Kernel
Query processing on multi-core architectures
Algorithm libraries for multi-core processors
Communication security for distributed mixed-criticality systems
MCSTL: the multi-core standard template library
Network coding strategies for multi-core architectures
Scalable Consistency in the Multi-core Era
Sylvan: multi-core framework for decision diagrams
Network Coding Strategies for Multi-Core Architectures
SHAP — Scalable Multi-Core Java Bytecode Processor
Analysis of Inter-Chip Communication Patterns on Multi-Core Distributed Shared-Memory Computers
Multi-core symbolic bisimulation minimisation
parMERASA Multi-core RTOS Kernel
Query processing on multi-core architectures
Algorithm libraries for multi-core processors
Communication security for distributed mixed-criticality systems
MCSTL: the multi-core standard template library
Network coding strategies for multi-core architectures
Scalable Consistency in the Multi-core Era
Sylvan: multi-core framework for decision diagrams
Network Coding Strategies for Multi-Core Architectures
SHAP — Scalable Multi-Core Java Bytecode Processor
Analysis of Inter-Chip Communication Patterns on Multi-Core Distributed Shared-Memory Computers
Multi-core symbolic bisimulation minimisation
parMERASA Multi-core RTOS Kernel
Query processing on multi-core architectures
Algorithm libraries for multi-core processors
Communication security for distributed mixed-criticality systems
MCSTL: the multi-core standard template library
Network coding strategies for multi-core architectures
Scalable Consistency in the Multi-core Era
Sylvan: multi-core framework for decision diagrams
Network Coding Strategies for Multi-Core Architectures