The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor
- Standort
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Deutsche Nationalbibliothek Frankfurt am Main
- ISSN
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1556-276X
- Umfang
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Online-Ressource
- Sprache
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Englisch
- Anmerkungen
-
online resource.
- Erschienen in
-
The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor ; volume:13 ; number:1 ; day:5 ; month:3 ; year:2018 ; pages:1-9 ; date:12.2018
Nanoscale research letters ; 13, Heft 1 (5.3.2018), 1-9, 12.2018
- Klassifikation
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Ingenieurwissenschaften und Maschinenbau
- Urheber
-
Li, Wei
- Beteiligte Personen und Organisationen
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Liu, Hongxia
Wang, Shulong
Chen, Shupeng
Wang, Qianqiong
SpringerLink (Online service)
- DOI
-
10.1186/s11671-018-2483-8
- URN
-
urn:nbn:de:1111-201805112527
- Rechteinformation
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Letzte Aktualisierung
-
14.08.2025, 10:55 MESZ
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Beteiligte
- Li, Wei
- Liu, Hongxia
- Wang, Shulong
- Chen, Shupeng
- Wang, Qianqiong
- SpringerLink (Online service)
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