The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

to related objects

Location: Deutsche Nationalbibliothek Frankfurt am Main

ISSN: 1556-276X

Extent: Online-Ressource

Language: Englisch

Notes: online resource.

Bibliographic citation: The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor ; volume:13 ; number:1 ; day:5 ; month:3 ; year:2018 ; pages:1-9 ; date:12.2018
Nanoscale research letters ; 13, Heft 1 (5.3.2018), 1-9, 12.2018

Classification: Ingenieurwissenschaften und Maschinenbau

Creator: Li, Wei

Contributor: Liu, Hongxia
Wang, Shulong
Chen, Shupeng
Wang, Qianqiong
SpringerLink (Online service)

DOI: 10.1186/s11671-018-2483-8

URN: urn:nbn:de:1111-201805112527

Rights: Der Zugriff auf das Objekt ist unbeschränkt möglich.

Last update: 14.08.2025, 10:55 AM CEST

Data provider

This object is provided by:
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.

Show original at data provider

Associated

Li, Wei
Liu, Hongxia
Wang, Shulong
Chen, Shupeng
Wang, Qianqiong
SpringerLink (Online service)

Other Objects (12)

Influence of gate tunneling currents on switched capacitor integrators

Parametric oscillation and amplification with gate controlled capacitor-within-capacitor

Hochschulschrift

Einfluss von Gate-Tunnelströmen auf Switched-Capacitor-Schaltungen

Archivale

Dram

Graffiti | Streetart

BASS DRAM

Graffiti | Streetart

dRAM

Schriftgut

Dram. Gutachten

Hochschulschrift | Online-Publikation

Logic gates realized with spin dependent tunneling elements

Hochschulschrift

Interface characterization of metal gate MOS-structures and the application to DRAM-capacitors

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Hochschulschrift

Interface characterization of metal-gate MOS-structures and the application to DRAM-capacitors

SRAM und DRAM

Influence of gate tunneling currents on switched capacitor integrators

Parametric oscillation and amplification with gate controlled capacitor-within-capacitor

Hochschulschrift

Einfluss von Gate-Tunnelströmen auf Switched-Capacitor-Schaltungen

Archivale

Dram

Graffiti | Streetart

BASS DRAM

Graffiti | Streetart

dRAM

Schriftgut

Dram. Gutachten

Hochschulschrift | Online-Publikation

Logic gates realized with spin dependent tunneling elements

Hochschulschrift

Interface characterization of metal gate MOS-structures and the application to DRAM-capacitors

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Hochschulschrift

Interface characterization of metal-gate MOS-structures and the application to DRAM-capacitors

SRAM und DRAM

Influence of gate tunneling currents on switched capacitor integrators

Parametric oscillation and amplification with gate controlled capacitor-within-capacitor

Hochschulschrift

Einfluss von Gate-Tunnelströmen auf Switched-Capacitor-Schaltungen

Archivale

Dram

Graffiti | Streetart

BASS DRAM

Graffiti | Streetart

dRAM

Schriftgut

Dram. Gutachten

Hochschulschrift | Online-Publikation

Logic gates realized with spin dependent tunneling elements

Hochschulschrift

Interface characterization of metal gate MOS-structures and the application to DRAM-capacitors

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Hochschulschrift

Interface characterization of metal-gate MOS-structures and the application to DRAM-capacitors

SRAM und DRAM

Cultural heritage institutions wishing to register will find more information here.

Fields marked * need to be filled in.

Username*

Please enter your username

Email*

Please enter your email address

Please do not fill this field

First name

Last name

Password*

Please enter your password

Confirm password*

Please enter the same password

I have read the terms of use and the privacy policy for the collection of personal data and accept them. *

This field is required.

I would like to subscribe to the newsletter of the Deutsche Digitale Bibliothek. See newsletter subscription info.

Account created

Your "My DDB" account has been successfully created. Before you can log in to your account, you must click the confirmation link in the message we just sent to the email address you provided.

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

Object Details

References and Relationships

Classification and Topics

Contributors, Places and Time

Further information

Data provider

Associated

Other Objects (12)

Influence of gate tunneling currents on switched capacitor integrators

Parametric oscillation and amplification with gate controlled capacitor-within-capacitor

Einfluss von Gate-Tunnelströmen auf Switched-Capacitor-Schaltungen

Dram

BASS DRAM

dRAM

Dram. Gutachten

Logic gates realized with spin dependent tunneling elements

Interface characterization of metal gate MOS-structures and the application to DRAM-capacitors

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Interface characterization of metal-gate MOS-structures and the application to DRAM-capacitors

SRAM und DRAM

Influence of gate tunneling currents on switched capacitor integrators

Parametric oscillation and amplification with gate controlled capacitor-within-capacitor

Einfluss von Gate-Tunnelströmen auf Switched-Capacitor-Schaltungen

Dram

BASS DRAM

dRAM

Dram. Gutachten

Logic gates realized with spin dependent tunneling elements

Interface characterization of metal gate MOS-structures and the application to DRAM-capacitors

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Interface characterization of metal-gate MOS-structures and the application to DRAM-capacitors

SRAM und DRAM

Influence of gate tunneling currents on switched capacitor integrators

Parametric oscillation and amplification with gate controlled capacitor-within-capacitor

Einfluss von Gate-Tunnelströmen auf Switched-Capacitor-Schaltungen

Dram

BASS DRAM

dRAM

Dram. Gutachten

Logic gates realized with spin dependent tunneling elements

Interface characterization of metal gate MOS-structures and the application to DRAM-capacitors

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Interface characterization of metal-gate MOS-structures and the application to DRAM-capacitors

SRAM und DRAM

Related objects

Reset password