Another Evidence to not Employ Customized Masked Hardware : Identifying and Fixing Flaws in SCARV

Abstract: As a well-studied countermeasure against side-channel analysis attacks, there is a general interest in applying masking to different cryptographic functions executed on different platforms. On the one hand, despite their high performance, masked hardware implementations are dedicated to specific algorithms, making them inflexible. On the other hand, applying masking on software involves serious challenges including significant overhead in terms of efficiency and difficulties to maintain theoretical security guarantees in practice. As a result, a line of research has been devoted to enable masked operations in flexible platforms (i.e., microprocessors) by including some masked modules in their hardware, hence a combination of flexibility and performance. In such scenarios, RISC-V is a natural choice as hardware can be adjusted to the extended instruction set. One such attempt presented at CHES 2021 is known as SCARV, which extends the Instruction Set Architecture (ISA) of a RISC-V c.... https://tches.iacr.org/index.php/TCHES/article/view/11786

Object Details

• Location: Deutsche Nationalbibliothek Frankfurt am Main
• Extent: Online-Ressource
• Language: Englisch

References and Relationships

• Bibliographic citation: Another Evidence to not Employ Customized Masked Hardware ; volume:2024 ; number:4 ; year:2024 ; IACR transactions on cryptographic hardware and embedded systems ; 2024, Heft 4 (2024)

Contributors, Places and Time

• Creator: Uhle, Felix ; Stolz, Florian ; Moradi, Amir

Further information

• DOI: 10.46586/tches.v2024.i4.133-155
• URN: urn:nbn:de:101:1-2409251857147.614286243477
• Rights: Open Access; Der Zugriff auf das Objekt ist unbeschränkt möglich.
• Last update: 15.08.2025, 7:35 AM CEST