Implementation and Design of FIR Filters using Verilog HDL and FPGA

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Location: Deutsche Nationalbibliothek Frankfurt am Main

Extent: Online-Ressource

Language: Englisch

Bibliographic citation: Implementation and Design of FIR Filters using Verilog HDL and FPGA ; volume:4 ; number:5 ; year:2020 ; pages:85-88 ; August
Perspectives in Communication, Embedded-Systems and Signal-Processing (PiCES) ; 4, Heft 5 (2020), 85-88, August

Classification: Elektrotechnik, Elektronik

Creator: Ramesh, Akshitha V.
Kumar, Apeksha Ravi
Iyengar, Amulya S.
B, Lekha Yadav

Contributor: Department of Electronics and Communication Engineering, KS Institute of Technology, Bangalore, India

URN: urn:nbn:de:101:1-2020090722021229995145

Rights: Der Zugriff auf das Objekt ist unbeschränkt möglich.

Last update: 14.08.2025, 10:57 AM CEST

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Ramesh, Akshitha V.
Kumar, Apeksha Ravi
Iyengar, Amulya S.
B, Lekha Yadav
Department of Electronics and Communication Engineering, KS Institute of Technology, Bangalore, India

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Implementation and Design of FIR Filters using Verilog HDL and FPGA

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