Nibbling MAYO: Optimized Implementations for AVX2 and Cortex-M4
Abstract: MAYO is a popular high-calorie condiment as well as an auspicious candidate in the ongoing NIST competition for additional post-quantum signature schemes achieving competitive signature and public key sizes. In this work, we present high-speed implementations of MAYO using the AVX2 and Armv7E-M instruction sets targeting recent x86 platforms and the Arm Cortex-M4. Moreover, the main contribution of our work is showing that MAYO can be even faster when switching from a bitsliced representation of keys to a nibble-sliced representation. While the bitsliced representation was primarily motivated by faster arithmetic on microcontrollers, we show that it is not necessary for achieving high performance on Cortex-M4. On Cortex-M4, we instead propose to implement the large matrix multiplications of MAYO using the Method of the Four Russians (M4R), which allows us to achieve better performance than when using the bitsliced approach. This results in up to 21% faster signing. For AVX2, the ch.... https://tches.iacr.org/index.php/TCHES/article/view/11427
- Location
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Deutsche Nationalbibliothek Frankfurt am Main
- Extent
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Online-Ressource
- Language
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Englisch
- Bibliographic citation
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Nibbling MAYO: Optimized Implementations for AVX2 and Cortex-M4 ; volume:2024 ; number:2 ; year:2024
IACR transactions on cryptographic hardware and embedded systems ; 2024, Heft 2 (2024)
- Creator
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Beullens, Ward
Campos, Fabio
Celi, Sofía
Hess, Basil
Kannwischer, Matthias J.
- DOI
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10.46586/tches.v2024.i2.252-275
- URN
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urn:nbn:de:101:1-2024032018001073860517
- Rights
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Open Access; Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
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14.08.2025, 10:44 AM CEST
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Associated
- Beullens, Ward
- Campos, Fabio
- Celi, Sofía
- Hess, Basil
- Kannwischer, Matthias J.
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MulLeak: Exploiting Multiply Instruction Leakage to Attack the Stack-optimized Kyber Implementation on Cortex-M4
Multi-moduli NTTs for Saber on Cortex-M3 and Cortex-M4
Classic McEliece on the ARM Cortex-M4
Cortex-M4 optimizations for R,M} LWE schemes
From SDL specifications to optimized parallel protocol implementations
Optimizing BIKE for the Intel Haswell and ARM Cortex-M4
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