Using Palladio network links to model multicore architecture memory hierarchies
- Location
-
Deutsche Nationalbibliothek Frankfurt am Main
- Extent
-
Online-Ressource
- Language
-
Englisch
- Event
-
Veröffentlichung
- (where)
-
Stuttgart
- (who)
-
Universitätsbibliothek der Universität Stuttgart
- (when)
-
2019
- Creator
-
Gruber, Philipp
- DOI
-
10.18419/opus-10676
- URN
-
urn:nbn:de:bsz:93-opus-ds-106933
- Rights
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
-
25.03.2025, 1:52 PM CET
Data provider
This object is provided by:
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Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Associated
- Gruber, Philipp
- Universitätsbibliothek der Universität Stuttgart
Time of origin
- 2019
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Energy conservation in memory hierarchies using Power-Aware Cached-DRAM
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Abstractions for performance programming on multi-core architectures with hierarchial memory
Abstractions for Performance Programming on Multi-Core Architectures with Hierarchical Memory
Vorgehensweise für die Multicore-Softwareentwicklung : [MWARE, multicore software]
Connecting Palladio with multicore CPU simulators
Algorithms for memory hierarchies : advanced lectures
Network Coding Strategies for Multi-Core Architectures
Network coding strategies for multi-core architectures
Exploiting multi-core systems for parallel network simulation
Reconstructing Bounding Volume Hierarchies from Memory Traces of Ray Tracers
Energy conservation in memory hierarchies using Power-Aware Cached-DRAM
Some experiments on tiling loop programs for shared memory multicore architectures
BriskStream: Scaling Data Stream Processing on Shared-Memory Multicore Architectures
Abstractions for performance programming on multi-core architectures with hierarchial memory
Abstractions for Performance Programming on Multi-Core Architectures with Hierarchical Memory
Vorgehensweise für die Multicore-Softwareentwicklung : [MWARE, multicore software]
Connecting Palladio with multicore CPU simulators
Algorithms for memory hierarchies : advanced lectures
Network Coding Strategies for Multi-Core Architectures
Network coding strategies for multi-core architectures
Exploiting multi-core systems for parallel network simulation
Reconstructing Bounding Volume Hierarchies from Memory Traces of Ray Tracers
Energy conservation in memory hierarchies using Power-Aware Cached-DRAM
Some experiments on tiling loop programs for shared memory multicore architectures
BriskStream: Scaling Data Stream Processing on Shared-Memory Multicore Architectures
Abstractions for performance programming on multi-core architectures with hierarchial memory
Abstractions for Performance Programming on Multi-Core Architectures with Hierarchical Memory