A Low-Power Squaring Circuit with Regulated Output and Improved Settling Time in 180 nm CMOS for 3–5 GHz IR-UWB Applications

Abstract. g m and, as a result, the quadratic term in the transfer function reaches a maximum. A control loop was implemented to set the dc output voltage to a defined value and thus to allow a comparison of the squarer output signal with a defined threshold voltage, which can easily be set and adjusted (e.g. by a DAC). To speed up the settling time of the output and hence to reach higher data rates, a novel slew-rate booster is implemented at the output. Thereby, the squarer is capable of data rates of up to 15.6 Mbit s−1, which is more than two times higher compared to the circuit without the slew-rate booster, while only consuming 72.4 µW in addition. In the extracted post-layout simulations the whole circuitry consumes 724 µA at a 1.8 V power supply, resulting in a power consumption of 1.3 mW.

Location
Deutsche Nationalbibliothek Frankfurt am Main
Extent
Online-Ressource
Language
Englisch

Bibliographic citation
A Low-Power Squaring Circuit with Regulated Output and Improved Settling Time in 180 nm CMOS for 3–5 GHz IR-UWB Applications ; volume:19 ; year:2021 ; pages:79-84 ; extent:6
Advances in radio science ; 19 (2021), 79-84 (gesamt 6)

Classification
Elektrotechnik, Elektronik

Creator
Schrüfer, Daniel
Röber, Jürgen
Mai, Timo
Weigel, Robert

DOI
10.5194/ars-19-79-2021
URN
urn:nbn:de:101:1-2021122304281774958333
Rights
Open Access; Der Zugriff auf das Objekt ist unbeschränkt möglich.
Last update
15.08.2025, 7:23 AM CEST

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Associated

  • Schrüfer, Daniel
  • Röber, Jürgen
  • Mai, Timo
  • Weigel, Robert

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