A Low-Latency High-Order Arithmetic to Boolean Masking Conversion
Abstract: Masking, an effective countermeasure against side-channel attacks, is commonly applied in modern cryptographic implementations. Considering cryptographic algorithms that utilize both Boolean and arithmetic masking, the conversion algorithm between arithmetic masking and Boolean masking is required. Conventional high-order arithmetic masking to Boolean masking conversion algorithms based on Boolean circuits suffer from performance overhead, especially in terms of hardware implementation. In this work, we analyze high latency for the conversion and propose an improved high-order A2B conversion algorithm. For the conversion of 16-bit variables, the hardware latency can be reduced by 47% in the best scenario. For the case study of second-order 32-bit conversion, the implementation results show that the improved scheme reduces the clock cycle latency by 42% in hardware and achieves a 30% speed performance improvement in software. Theoretically, a security proof of arbitrary order is pro.... https://tches.iacr.org/index.php/TCHES/article/view/11441
- Location
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Deutsche Nationalbibliothek Frankfurt am Main
- Extent
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Online-Ressource
- Language
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Englisch
- Bibliographic citation
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A Low-Latency High-Order Arithmetic to Boolean Masking Conversion ; volume:2024 ; number:2 ; year:2024
IACR transactions on cryptographic hardware and embedded systems ; 2024, Heft 2 (2024)
- Creator
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Liu, Jiangxue
Zhao, Cankun
Peng, Shuohang
Yang, Bohan
Zhao, Hang
Han, Xiangdong
Zhu, Min
Wei, Shaojun
Liu, Leibo
- DOI
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10.46586/tches.v2024.i2.630-653
- URN
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urn:nbn:de:101:1-2024032017580961400225
- Rights
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Open Access; Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
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14.08.2025, 10:44 AM CEST
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Associated
- Liu, Jiangxue
- Zhao, Cankun
- Peng, Shuohang
- Yang, Bohan
- Zhao, Hang
- Han, Xiangdong
- Zhu, Min
- Wei, Shaojun
- Liu, Leibo
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