Analyse von Test-Pattern für SoC Multiprozessortest und -debugging mittels Test Access Port (JTAG)

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Location: Deutsche Nationalbibliothek Frankfurt am Main

Extent: Online-Ressource

Language: Deutsch

Notes: In: Dresdner Arbeitstagung Schaltungs- und Systementwurf - Band 5

Classification: Elektrotechnik, Elektronik

Keyword: Field programmable gate array
Abtastung
Logikanalysator
Statistischer Test
Kommunikationsprotokoll
Eingebettetes System
Kommunikationsprotokoll

Event: Veröffentlichung

(where): Chemnitz

(who): Universitätsbibliothek Chemnitz

(when): 2007

Event: Veröffentlichung

(where): Chemnitz

(who): Technische Universität Chemnitz

(when): 2007

Creator: Vogelsang, Stefan
Köhler, Steffen
Spallek, Rainer G.

Contributor: Hardt, Wolfram

URN: urn:nbn:de:swb:ch1-200701007

Rights: Der Zugriff auf das Objekt ist unbeschränkt möglich.

Last update: 14.08.2025, 11:02 AM CEST

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Associated

Vogelsang, Stefan
Köhler, Steffen
Spallek, Rainer G.
Hardt, Wolfram
Universitätsbibliothek Chemnitz
Technische Universität Chemnitz

Time of origin

2007

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Analyse von Test-Pattern für SoC Multiprozessortest und -debugging mittels Test Access Port (JTAG)

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Associated

Time of origin

Other Objects (12)

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