Low-latency design and implementation of the squaring in class groups for verifiable delay function using redundant representation
- Standort
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Deutsche Nationalbibliothek Frankfurt am Main
- Umfang
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Online-Ressource
- Sprache
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Englisch
- Erschienen in
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Low-latency design and implementation of the squaring in class groups for verifiable delay function using redundant representation ; volume:2023 ; number:1 ; pages:438-462
IACR transactions on cryptographic hardware and embedded systems ; 2023, Heft 1, 438-462
- Klassifikation
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Informatik
- Urheber
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Zhu, Danyang
Zhang, Rongrong
Ou, Lun
Tian, Jing
Wang, Zhongfeng
- DOI
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10.46586/tches.v2023.i1.438-462
- URN
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urn:nbn:de:hbz:294-TCHES-3259
- Rechteinformation
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Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Letzte Aktualisierung
- 14.08.2025, 11:00 MESZ
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Beteiligte
- Zhu, Danyang
- Zhang, Rongrong
- Ou, Lun
- Tian, Jing
- Wang, Zhongfeng
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