Hardening Digital Circuits against Invasive Attacks with On-Chip Delay Measurements
- Alternative title
-
Härtung digitaler Schaltungen gegen invasive Angriffe mittels chipinterner Laufzeitmessungen
- Location
-
Deutsche Nationalbibliothek Frankfurt am Main
- Extent
-
Online-Ressource
- Language
-
Englisch
- Notes
-
München, Technische Universität München, Dissertation, 2020
- Classification
-
Elektrotechnik, Elektronik
- Keyword
-
Digital electronics
El Salvador
Barcelona
- Event
-
Veröffentlichung
- (where)
-
München
- (who)
-
Universitätsbibliothek der TU München
- (when)
-
2020
- Creator
-
Weiner, Michael
- Contributor
-
Sigl, Georg
Manich Bou, Salvador
Sigl, Georg
- URN
-
urn:nbn:de:bvb:91-diss-20201204-1547380-1-7
- Rights
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
-
25.03.2025, 1:43 PM CET
Data provider
This object is provided by:
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Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Associated
- Weiner, Michael
- Sigl, Georg
- Manich Bou, Salvador
- Universitätsbibliothek der TU München
Time of origin
- 2020
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USB borne attacks and usable defense mechanisms: Hardening built into the operating system without compromising on usability
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Nonblocking On-Chip Interconnection Networks
The history of hardening
Submillimeter-wave monolithic integrated circuits with metastructure-based on-chip antennas
On-chip ESD protection in integrated circuits : device physics, modeling, circuit simulation
Microfluidic chemical integrated circuits based on stimuli-responsive hydrogels for on-chip flow control
Analysis of On-Chip Inductors and Arithmetic Circuits in the Context of High Performance Computing
Fully integrated BiCMOS high-voltage driver circuits for on-chip RF-MEMS switch matrices
Laser-based attacks on secure integrated circuits : extracting and protecting sensitive information
Flame Hardening
Differential power-analysis attacks : a practical example for hardware countermeasures protecting cryptographic circuits
USB borne attacks and usable defense mechanisms: Hardening built into the operating system without compromising on usability
Accurate power estimation of deep-submicron VLSI circuits considering delay effects and glitches
Nonblocking On-Chip Interconnection Networks