- Weitere Titel
-
Beschleunigung approximativer Datenanalyse durch parallele Prozessoren
- Standort
-
Deutsche Nationalbibliothek Frankfurt am Main
- Umfang
-
Online-Ressource
- Sprache
-
Englisch
- Anmerkungen
-
Berlin, Technische Universität Berlin, Dissertation, 2023
- Schlagwort
-
Field programmable gate array
Parallelverarbeitung
Schätzung
- Ereignis
-
Veröffentlichung
- (wo)
-
Berlin
- (wer)
-
Technische Universität Berlin
- (wann)
-
2023
- Urheber
- Beteiligte Personen und Organisationen
-
Markl, Volker
István, Zsolt
Teubner, Jens
Tzirita Zacharatou, Eleni
- DOI
-
10.14279/depositonce-17124
- Handle
-
11303/18316
- URN
-
urn:nbn:de:101:1-2023041902012606894970
- Rechteinformation
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Letzte Aktualisierung
-
25.03.2024, 14:23 MEZ
Datenpartner
Dieses Objekt wird bereitgestellt von:
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Beteiligte
- Kiefer, Martin
- Markl, Volker
- István, Zsolt
- Teubner, Jens
- Tzirita Zacharatou, Eleni
- Technische Universität Berlin
Entstanden
- 2023
Ähnliche Objekte (12)
Accelerating HPC applications with Out-of-Order Commit Processors
Compilation for instruction parallel processors
Approximate time-parallel simulation
A parallelizing compiler for distributed memory parallel processors
Parallel reversal schedules using more checkpoints than processors
Volume driven selection of loop and data transformations for cache coherent parallel processors
Approximate and Reconfigurable Precision Instruction Set Processors for Tightly Coupled Processor Arrays
Parallel delaunay mesh generation using multiple graphic card processors
Accelerating the molecular dynamics program LAMMPS using graphics cards' processors and the Nvidia Cuda technology
Approximate Data Analytics Systems
Modified sparse approximate inverses (MSPAI) for parallel preconditioning
The architecture of high performance processors and their applicability to parallel systems
Accelerating HPC applications with Out-of-Order Commit Processors
Compilation for instruction parallel processors
Approximate time-parallel simulation
A parallelizing compiler for distributed memory parallel processors
Parallel reversal schedules using more checkpoints than processors
Volume driven selection of loop and data transformations for cache coherent parallel processors
Approximate and Reconfigurable Precision Instruction Set Processors for Tightly Coupled Processor Arrays
Parallel delaunay mesh generation using multiple graphic card processors
Accelerating the molecular dynamics program LAMMPS using graphics cards' processors and the Nvidia Cuda technology
Approximate Data Analytics Systems
Modified sparse approximate inverses (MSPAI) for parallel preconditioning
The architecture of high performance processors and their applicability to parallel systems
Accelerating HPC applications with Out-of-Order Commit Processors
Compilation for instruction parallel processors
Approximate time-parallel simulation
A parallelizing compiler for distributed memory parallel processors
Parallel reversal schedules using more checkpoints than processors
Volume driven selection of loop and data transformations for cache coherent parallel processors
Approximate and Reconfigurable Precision Instruction Set Processors for Tightly Coupled Processor Arrays
Parallel delaunay mesh generation using multiple graphic card processors
Accelerating the molecular dynamics program LAMMPS using graphics cards' processors and the Nvidia Cuda technology
Approximate Data Analytics Systems
Modified sparse approximate inverses (MSPAI) for parallel preconditioning