- Location
-
Deutsche Nationalbibliothek Frankfurt am Main
- Extent
-
Online-Ressource
- Language
-
Deutsch
- Bibliographic citation
-
Berichte des Fraunhofer-Instituts für Techno- und Wirtschaftsmathematik (ITWM Report) ; 97
- Classification
-
Mathematik
- Event
-
Veröffentlichung
- (where)
-
Kaiserslautern
- (who)
-
Fraunhofer-Institut für Techno- und Wirtschaftsmathematik, Fraunhofer (ITWM)
- (when)
-
2006
- Creator
-
Dreyer, A.
- URN
-
urn:nbn:de:hbz:386-kluedo-14605
- Rights
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
-
25.03.2025, 1:46 PM CET
Data provider
This object is provided by:
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Associated
- Dreyer, A.
- Fraunhofer-Institut für Techno- und Wirtschaftsmathematik, Fraunhofer (ITWM)
Time of origin
- 2006
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Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
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Analog electronic circuits
Interval methods for numerical computation :
Formal verification methodologies for nonlinear analog circuits
Formal verification methodologies for nonlinear analog circuits
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
Aging-Aware Design Methods for Reliable Analog Integrated Circuits using Operating Point-Dependent Degradation
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
User controlled layout synthesis for analog integrated circuits
User-controlled layout synthesis for analog integrated circuits
Symbolic methods for testing digital circuits
Symbolic methods for testing digital circuits
Analog electronic circuits
Interval methods for numerical computation :
Formal verification methodologies for nonlinear analog circuits
Formal verification methodologies for nonlinear analog circuits
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
Aging-Aware Design Methods for Reliable Analog Integrated Circuits using Operating Point-Dependent Degradation
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
User controlled layout synthesis for analog integrated circuits
User-controlled layout synthesis for analog integrated circuits
Symbolic methods for testing digital circuits