- Standort
-
Deutsche Nationalbibliothek Frankfurt am Main
- Umfang
-
Online-Ressource
- Sprache
-
Deutsch
- Erschienen in
-
Berichte des Fraunhofer-Instituts für Techno- und Wirtschaftsmathematik (ITWM Report) ; 97
- Klassifikation
-
Mathematik
- Ereignis
-
Veröffentlichung
- (wo)
-
Kaiserslautern
- (wer)
-
Fraunhofer-Institut für Techno- und Wirtschaftsmathematik, Fraunhofer (ITWM)
- (wann)
-
2006
- Urheber
-
Dreyer, A.
- URN
-
urn:nbn:de:hbz:386-kluedo-14605
- Rechteinformation
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Letzte Aktualisierung
-
25.03.2025, 13:46 MEZ
Datenpartner
Dieses Objekt wird bereitgestellt von:
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Beteiligte
- Dreyer, A.
- Fraunhofer-Institut für Techno- und Wirtschaftsmathematik, Fraunhofer (ITWM)
Entstanden
- 2006
Ähnliche Objekte (12)
Analog electronic circuits
Interval methods for numerical computation :
Formal verification methodologies for nonlinear analog circuits
Formal verification methodologies for nonlinear analog circuits
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
Aging-Aware Design Methods for Reliable Analog Integrated Circuits using Operating Point-Dependent Degradation
User-controlled layout synthesis for analog integrated circuits
User controlled layout synthesis for analog integrated circuits
Symbolic methods for testing digital circuits
Symbolic methods for testing digital circuits
Analog electronic circuits
Interval methods for numerical computation :
Formal verification methodologies for nonlinear analog circuits
Formal verification methodologies for nonlinear analog circuits
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
Aging-Aware Design Methods for Reliable Analog Integrated Circuits using Operating Point-Dependent Degradation
User-controlled layout synthesis for analog integrated circuits
User controlled layout synthesis for analog integrated circuits
Symbolic methods for testing digital circuits
Symbolic methods for testing digital circuits
Analog electronic circuits
Interval methods for numerical computation :
Formal verification methodologies for nonlinear analog circuits
Formal verification methodologies for nonlinear analog circuits
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis
Aging-Aware Design Methods for Reliable Analog Integrated Circuits using Operating Point-Dependent Degradation
User-controlled layout synthesis for analog integrated circuits
User controlled layout synthesis for analog integrated circuits
Symbolic methods for testing digital circuits