Enhancing active model learning with equivalence checking using simulation relations

to related objects

Location: Deutsche Nationalbibliothek Frankfurt am Main

Extent: Online-Ressource, 1 online resource.

Language: Englisch

Bibliographic citation: Enhancing active model learning with equivalence checking using simulation relations ; day:6 ; month:8 ; year:2023 ; pages:1-34
Formal methods in system design ; (6.8.2023), 1-34

Creator: Yogananda Jeppu, Natasha
Melham, Tom
Kroening, Daniel

Contributor: SpringerLink (Online service)

DOI: 10.1007/s10703-023-00433-y

URN: urn:nbn:de:101:1-2023110207483227041274

Rights: Open Access; Der Zugriff auf das Objekt ist unbeschränkt möglich.

Last update: 14.08.2025, 10:53 AM CEST

Data provider

This object is provided by:
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.

Show original at data provider

Associated

Yogananda Jeppu, Natasha
Melham, Tom
Kroening, Daniel
SpringerLink (Online service)

Other Objects (12)

Hochschulschrift

Formal sequential equivalence checking of digital systems by symbolic simulation

Hochschulschrift | Online-Publikation

Formal sequential equivalence checking of digital systems by symbolic simulation

Equivalence checking of quantum circuits by nonlocality

Publisher Correction: Equivalence checking of quantum circuits by nonlocality

Enhancing Probabilistic Model Checking with Ontologies

Equivalence checking and intersection of deterministic timed finite state machines

Enhancing symbolic model checking by AI techniques

System Verification Via Generic Games : Behavioural Equivalence and Model Checking Games

Hochschulschrift

Using decision diagrams in the design of reversible circuit : embedding - synthesis - debugging - equivalence checking

Liveness checking as safety checking

Symbolic Causality Checking Using Bounded Model Checking

Hochschulschrift

Formal sequential equivalence checking of digital systems by symbolic simulation

Hochschulschrift | Online-Publikation

Formal sequential equivalence checking of digital systems by symbolic simulation

Equivalence checking of quantum circuits by nonlocality

Publisher Correction: Equivalence checking of quantum circuits by nonlocality

Enhancing Probabilistic Model Checking with Ontologies

Equivalence checking and intersection of deterministic timed finite state machines

Enhancing symbolic model checking by AI techniques

System Verification Via Generic Games : Behavioural Equivalence and Model Checking Games

Hochschulschrift

Using decision diagrams in the design of reversible circuit : embedding - synthesis - debugging - equivalence checking

Liveness checking as safety checking

Symbolic Causality Checking Using Bounded Model Checking

Hochschulschrift

Formal sequential equivalence checking of digital systems by symbolic simulation

Hochschulschrift | Online-Publikation

Formal sequential equivalence checking of digital systems by symbolic simulation

Equivalence checking of quantum circuits by nonlocality

Publisher Correction: Equivalence checking of quantum circuits by nonlocality

Enhancing Probabilistic Model Checking with Ontologies

Equivalence checking and intersection of deterministic timed finite state machines

Enhancing symbolic model checking by AI techniques

System Verification Via Generic Games : Behavioural Equivalence and Model Checking Games

Hochschulschrift

Using decision diagrams in the design of reversible circuit : embedding - synthesis - debugging - equivalence checking

Liveness checking as safety checking

Symbolic Causality Checking Using Bounded Model Checking

Cultural heritage institutions wishing to register will find more information here.

Fields marked * need to be filled in.

Username*

Please enter your username

Email*

Please enter your email address

Please do not fill this field

First name

Last name

Password*

Please enter your password

Confirm password*

Please enter the same password

I have read the terms of use and the privacy policy for the collection of personal data and accept them. *

This field is required.

I would like to subscribe to the newsletter of the Deutsche Digitale Bibliothek. See newsletter subscription info.

Account created

Your "My DDB" account has been successfully created. Before you can log in to your account, you must click the confirmation link in the message we just sent to the email address you provided.

Enhancing active model learning with equivalence checking using simulation relations

Object Details

References and Relationships

Contributors, Places and Time

Further information

Data provider

Associated

Other Objects (12)

Formal sequential equivalence checking of digital systems by symbolic simulation

Formal sequential equivalence checking of digital systems by symbolic simulation

Equivalence checking of quantum circuits by nonlocality

Publisher Correction: Equivalence checking of quantum circuits by nonlocality

Enhancing Probabilistic Model Checking with Ontologies

Equivalence checking and intersection of deterministic timed finite state machines

Enhancing symbolic model checking by AI techniques

System Verification Via Generic Games : Behavioural Equivalence and Model Checking Games

Using decision diagrams in the design of reversible circuit : embedding - synthesis - debugging - equivalence checking

Liveness checking as safety checking

Symbolic Causality Checking Using Bounded Model Checking

Symbolic Causality Checking Using Bounded Model Checking

Formal sequential equivalence checking of digital systems by symbolic simulation

Formal sequential equivalence checking of digital systems by symbolic simulation

Equivalence checking of quantum circuits by nonlocality

Publisher Correction: Equivalence checking of quantum circuits by nonlocality

Enhancing Probabilistic Model Checking with Ontologies

Equivalence checking and intersection of deterministic timed finite state machines

Enhancing symbolic model checking by AI techniques

System Verification Via Generic Games : Behavioural Equivalence and Model Checking Games

Using decision diagrams in the design of reversible circuit : embedding - synthesis - debugging - equivalence checking

Liveness checking as safety checking

Symbolic Causality Checking Using Bounded Model Checking

Symbolic Causality Checking Using Bounded Model Checking

Formal sequential equivalence checking of digital systems by symbolic simulation

Formal sequential equivalence checking of digital systems by symbolic simulation

Equivalence checking of quantum circuits by nonlocality

Publisher Correction: Equivalence checking of quantum circuits by nonlocality

Enhancing Probabilistic Model Checking with Ontologies

Equivalence checking and intersection of deterministic timed finite state machines

Enhancing symbolic model checking by AI techniques

System Verification Via Generic Games : Behavioural Equivalence and Model Checking Games

Using decision diagrams in the design of reversible circuit : embedding - synthesis - debugging - equivalence checking

Liveness checking as safety checking

Symbolic Causality Checking Using Bounded Model Checking

Symbolic Causality Checking Using Bounded Model Checking

Related objects

Reset password