Hochschulschrift
SmartMem : An Advanced Memory Subsystem for Networking Applications
- Alternative title
-
SmartMem
- Location
-
Deutsche Nationalbibliothek Frankfurt am Main
- Extent
-
Online-Ressource
- Language
-
Englisch
- Notes
-
München, Technische Universität München, Diss., 2012
- Event
-
Veröffentlichung
- (where)
-
München
- (who)
-
Universitätsbibliothek der TU München
- (when)
-
2012
- Creator
- Contributor
- URN
-
urn:nbn:de:bvb:91-diss-20120423-1084159-1-5
- Rights
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Last update
-
15.08.2025, 7:34 AM CEST
Data provider
This object is provided by:
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Deutsche Nationalbibliothek. If you have any questions about the object, please contact the data provider.
Object type
- Hochschulschrift
Associated
- Llorente Sancho, Daniel
- Herkersdorf, Andreas
- Schmitt-Landsiedel, Doris
- Universitätsbibliothek der TU München
Time of origin
- 2012
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Fast and accurate performance simulation of out-of-order processing cores in embedded systems
A cycle-accurate coprocessor prototyping platform for system-on-chip
A Network Processor Architecture for High Speed Carrier Grade Ethernet Networks
Network on Chip Interface for Scalable Distributed Shared Memory Architectures
Memory Efficient Signature Matching in Deep Packet Inspection Applications at Line Rates
The Impact of Architecture on Quality of Electronic Control Systems : The Cost of Architectural Complexity
Dependable and Energy-Efficient Mixed-Critical Real-Time Systems-on-Chip
Enablement of Multi-Core-Based Automotive Embedded Systems through I/O- and Network Virtualization
Flexible Verwaltung von Tasks zur Selbst-Adaption von gemischtkritischen Systemen anhand eines automotiven Beispiels
On Fault Resilient Network-on-Chip for Many Core Systems
Near-Memory Acceleration of Inter-Process Communication on Tile-Based Many-Core Architectures
SmartMem : an advanced memory subsystem for networking applications
Fast and accurate performance simulation of out-of-order processing cores in embedded systems
A cycle-accurate coprocessor prototyping platform for system-on-chip
A Network Processor Architecture for High Speed Carrier Grade Ethernet Networks
Network on Chip Interface for Scalable Distributed Shared Memory Architectures
Memory Efficient Signature Matching in Deep Packet Inspection Applications at Line Rates
The Impact of Architecture on Quality of Electronic Control Systems : The Cost of Architectural Complexity
Dependable and Energy-Efficient Mixed-Critical Real-Time Systems-on-Chip
Enablement of Multi-Core-Based Automotive Embedded Systems through I/O- and Network Virtualization
Flexible Verwaltung von Tasks zur Selbst-Adaption von gemischtkritischen Systemen anhand eines automotiven Beispiels
On Fault Resilient Network-on-Chip for Many Core Systems